IEC - International Electrotechnical Commission - IEC 62142:2005

Verilog (R) register transfer level synthesis

withdrawn
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Organization: IEC - International Electrotechnical Commission
Publication Date: 27 June 2005
Status: withdrawn
Page Count: 109
ICS Code (Other industrial automation systems): 25.040.99
abstract:

Defines a set of modeling rules for writing Verilog®

HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between... View More

Document History

IEC 62142:2005
June 27, 2005
Verilog (R) register transfer level synthesis
Defines a set of modeling rules for writing Verilog® HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer...
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