IEEE - Institute of Electrical and Electronics Engineers, Inc. - P1450.6.2/D6, Jul 2013
IEEE Draft Standard for Memory Modeling in Core Test Language (CTL)
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| Organization: | IEEE - Institute of Electrical and Electronics Engineers, Inc. |
| Publication Date: | 21 August 2013 |
| Status: | inactive |
| Page(s): | 1 - 73 |
| ICS Code (Languages used in information technology): | 35.060 |
| ISBN (Online): | 978-0-7381-8619-1 |
Standard:
System on Chip (SoC) test requires reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits. This activity defines language... View More
Document History
June 13, 2014
IEEE Draft Standard for Memory Modeling in Core Test Language (CTL)
System on Chip (SoC) test requires reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits. This activity defines language...
June 13, 2014
IEEE Standard for Memory Modeling in Core Test Language
Reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits is required for system-on-chip (SoC) tests. This standard defines...
P1450.6.2/D6, Jul 2013
August 21, 2013
IEEE Draft Standard for Memory Modeling in Core Test Language (CTL)
System on Chip (SoC) test requires reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits. This activity defines language...
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