IEEE - Institute of Electrical and Electronics Engineers, Inc. - 62530-2011
SystemVerilog Unified Hardware Design, Specification, and Verification Language
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| Organization: | IEEE - Institute of Electrical and Electronics Engineers, Inc. |
| Publication Date: | 19 May 2011 |
| Status: | active |
| Page(s): | 1 - 1,294 |
| ICS Code (Industrial automation systems): | 25.040 |
| ICS Code (Languages used in information technology): | 35.060 |
| ISBN (Online): | 978-0-7381-6607-0 |
| DOI: | 10.1109/IEEESTD.2011.5944940 |
Standard:
This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design,... View More
Document History
62530-2011
May 19, 2011
SystemVerilog Unified Hardware Design, Specification, and Verification Language
This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design,...
December 9, 2007
IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also...
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