IEEE - Institute of Electrical and Electronics Engineers, Inc. - 61691-4-2004
IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages - Part 4: Verilog(C) Hardware Description Language
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Organization: | IEEE - Institute of Electrical and Electronics Engineers, Inc. |
Publication Date: | 15 November 2004 |
Status: | inactive |
Page(s): | 1 - 879 |
ICS Code (Languages used in information technology): | 35.060 |
ISBN (Electronic): | 978-0-7381-4524-2 |
DOI: | 10.1109/IEEESTD.2004.95753 |
Standard:
The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is... View More
Document History

April 7, 2006
IEEE Standard for Verilog Hardware Description Language
The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both...

January 1, 2005
IEEE Unapproved IEEE Draft Standard for Verilog? Hardware Description Language (Revision of 1364-1995) Replaced by Approved IEEE Draft
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61691-4-2004
November 15, 2004
IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages - Part 4: Verilog(C) Hardware Description Language
The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is...

September 28, 2001
IEEE Standard Verilog Hardware Description Language
Supersedes 1364-1995. The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic...

October 14, 1996
IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language
The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable...