IEEE - Institute of Electrical and Electronics Engineers, Inc. - 1364.1-2002
IEEE Standard for Verilog Register Transfer Level Synthesis
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| Organization: | IEEE - Institute of Electrical and Electronics Engineers, Inc. |
| Publication Date: | 18 December 2002 |
| Status: | inactive |
| Page(s): | 1 - 108 |
| ICS Code (Languages used in information technology): | 35.060 |
| ISBN (Electronic): | 978-0-7381-3502-1 |
| DOI: | 10.1109/IEEESTD.2002.94220 |
Standard:
Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL... View More
Document History
January 1, 2005
Verilog Register Transfer Level Synthesis
A description is not available for this item.
1364.1-2002
December 18, 2002
IEEE Standard for Verilog Register Transfer Level Synthesis
Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL...
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