IEEE - Institute of Electrical and Electronics Engineers, Inc. - 960-1993

10. Interconnection of Segments

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Organization: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1994
Status: active
Page Count: 14
ISBN (Paper): 1-55937-396-2
ISBN (Online): 0-7381-0723-9
DOI: 10.1109/IEEESTD.1994.79584

Document History

January 1, 1994
IEEE Standard FASTBUS Modular High-Speed Data Acquisition and Control System and IEEE FASTBUS Standard Routines
A description is not available for this item.
January 1, 1994
1. Introduction and General Information
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January 1, 1994
4. FASTBUS Operations: Addressing
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January 1, 1994
5. FASTBUS Operations: Timing, Sequences and Responses
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January 1, 1994
6. Bus Arbitration
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January 1, 1994
7. Ancillary Logic on a Segment
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January 1, 1994
8. Control and Status Register Space
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January 1, 1994
9. Interrupts
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January 1, 1994
11. Block and Pipelined Transfers
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January 1, 1994
16. Cable Segment
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January 1, 1994
Annex A. Requirements for Various Implementations
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January 1, 1994
Annex B. Front Panel Interconnections for ECL
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January 1, 1994
Annex J. Non-Zero Status Handling Procedures
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January 1, 1994
Annex K. Components
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January 1, 1994
Annex N. Multi-Module Data Transfer Specification (MDT-1)
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January 1, 1994
Index
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January 1, 1994
IEEE FASTBUS Standard Routines
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January 1, 1994
1. Overview
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January 1, 1994
2. Basic Concepts
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January 1, 1994
5. Data Buffers
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January 1, 1994
6. Simple Transaction Routines
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January 1, 1994
7. Compound Transaction Routines
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January 1, 1994
8. Primitive FASTBUS Action Routines
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January 1, 1994
11. Status and Error Handling
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January 1, 1994
12. Error Codes
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