loading
The Silc™ Silicon Compiler: Language and Features
1985 Edition, January 1, 1985 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We describe the language and features of Silc™, a new silicon compiler. Silc™ takes an algorithmic description of a circuit, performs logic synthesis, optimization, and physical layout synthesis, and produces a mask-level...

Yet Another Silicon Compiler
1985 Edition, January 1, 1985 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, we describe the YASC high-level silicon compiler which synthesizes compact chip layouts from hierarchical behavioral descriptions. A logic synthesis procedure generates sets of Boolean equations, including multi-phase clocks and any necessary interface...

Feedback in silicon compilers
1985 Edition, Volume 1, May 1, 1985 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In order for silicon compilers to become a truly viable VLSI design option, application-specific information must be extracted and used as feedback to permit optimization of chip designs. The author describes three significant phases necessary to provide feedback in...

Designing Gate Arrays Using a Silicon Compiler
1982 Edition, January 1, 1982 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes a programming environment in which gate array designs can be developed. It allows the engineer to design for performance, wirability and testability by manipulating a textual description of a design. The principle features of this are a high-level...

An intelligent EPROM silicon compiler
1991 Edition, January 1, 1991 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The authors describe an intelligent EPROM silicon compiler. The compiler accepts high-level specifications of the required EPROM design together with technology and process information and produces CMOS mask geometries for all layers. A...

Silicon compiler for neuro-ASICs
1990 Edition, January 1, 1990 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A distributed, synchronous architecture for artificial neural networks is proposed. A basic processor is associated to a neuron and is able to perform autonomously all the steps of the learning and the relaxation phases. Data circulation is implemented by shifting...

A digital-serial silicon compiler
1988 Edition, January 1, 1988 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A novel silicon compiler is described, called PARSIFAL. It constructs chips with a data-flow architecture in which data is passed in a digit-wide pipeline form one computational element to the next. The size of a digit can be specified by the user to be any value...

Bristle Blocks: A Silicon Compiler
1979 Edition, January 1, 1979 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Standard LSI Design Automation systems are database management systems that aid the circuit designer by organizing the collection of submodules that comprise a chip. This type of file system usually does not aid in the actual computation of silicon layout, and can...

A Silicon Compiler for VLSI Signal Processors
1982 Edition, September 1, 1982 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper reports a silicon compiler that allows the rapid implementation of LSI/VLSI signal processors from a high level system description language.

GENERIC: A Silicon Compiler Support Language
1986 Edition, January 1, 1986 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We describe a support language, GENERIC, for producing high quality, general purpose layout in a silicon compiler. Since layout is the critical bottleneck to producing high-quality integrated circuits in silicon compilers, better methods are needed for this...

Advertisement