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The mathematical model & novel final test system for wafer-level packaging
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

To develop integrated circuit (IC) test of wafer-level-packaging, the electro-mechanical model of micro-probe testing process and IC final test system of wafer-level-packaging based on microprobe arrays is...

Foreword Wafer-Level Packaging
2007 Edition, Volume 30, August 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The four papers in this special section focus on wafer-level packaging. The selected papers cover the state-of-the-art and future development trends for wafer level chip scale packages (WLCSPs) by the leading...

Wafer level packaging of MEMS
2009 Edition, June 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Wafer level packaging methods of MEMS are described. These play important roles to reduce cost and to improve reliability. MEMS structures on silicon chips are encapsulated with bonded caps or with shells fabricated by surface micromachining, and electrical interconnections are...

Integrated sensor wafer-level packaging
1997 Edition, Volume 1, January 1, 1997 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Low cost packaging for integrated sensor devices is key to the ingress of silicon sensors into the consumer and industrial marketplace. Wafer-level packaging for integrated sensors can be performed using several technologies. The...

HMIC wafer level packaging
2009 Edition, September 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

HMIC, an acronym for heterolithic microwave integrated circuits, is fundamentally a wafer level substrate which combines low, RF loss tangent glass with micromachined silicon to produce three dimensional circuitry with the capability to make RF, DC, and thermal vias as...

HMIC wafer level packaging
2009 Edition, September 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

HMIC, an acronym for Heterolithic Microwave Integrated Circuits, is fundamentally a wafer level substrate which combines low, RF loss tangent glass with micromachined silicon to produce three dimensional circuitry with the capability to make RF, DC, and thermal vias as...

Advanced LED wafer level packaging technologies
2011 Edition, October 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Currently most LED components are made with individual chip packaging technology. The main manufacturing processes follow conventional chip-based IC packaging. In the past several years, there is an uprising trend in the IC industry to migrate from chip-based...

Foreword Wafer Level Packaging: More of Many
2008 Edition, Volume 31, February 1, 2008 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The five papers in this special section focus on wafer level packaging.

Wafer-level packaging technology for MEMS
2000 Edition, Volume 1, January 1, 2000 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper reviews the essential MEMS (Microelectromechanical Systems) silicon wafer processes that are needed for wafer-level packaging. Precision aligned wafer bonding is the key enabling technology for high-volume, low cost...

Worldwide markets for wafer level packages
2002 Edition, January 1, 2002 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

With increased demand for small form factor packages at low cost, wafer level packaging has emerged as the package of choice for many devices. Wafer level packages can be examined by package construction:...

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