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SEE characterization of the AMS 0.35 μm CMOS technology
2013 Edition, September 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents experimental results for the single-event effects characterization of a commercial (Austria Microsystems) 0.35 μm CMOS technology. It improves and expands previous results. The knowledge gained is being applied in the...

SEE characterization and mitigation in ultra-deep submicron technologies
2009 Edition, May 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

As technology feature sizes decrease, single event upset (SEU), digital single event transient (DSET), and multiple bit upset (MBU) effects dominate the radiation response of microcircuits in space applications. Even in high-altitude and terrestrial applications, cosmic-ray...

TID and SEE Characterization of Microsemi's 4th Generation Radiation Tolerant RTG4 Flash-Based FPGA
2015 Edition, July 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

TID and SEE characterization of Microsemi's 4th generation RTG4 flash-based FPGA is presented. The radiation performance of RTG4 is compared to SmartFusion2, Microsemi's 4th generation commercial flash-based FPGA.

SEE characterization of vertical DMOSFETs: an updated test protocol
2003 Edition, Volume 50, December 1, 2003 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The test protocols for power MOSFETs used in the manufacturer's specification sheets are inadequate in that they do not represent a realistic worst-case condition. In addition, the applicable single-event effects (SEE) test methods and guidelines do not provide...

SOI Substrate Removal for SEE Characterization: Techniques and Applications
2012 Edition, Volume 59, August 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Techniques for removing the back substrate of SOI devices are described for both packaged devices and devices at the die level. The use of these techniques for microbeam, heavy-ion, and laser testing are illustrated.

SOI substrate removal for SEE characterization: Techniques and applications
2011 Edition, September 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Techniques for removing the back substrate of SOI devices are described for both packaged devices and devices at the die level. The use of these techniques for microbeam, heavy-ion, and laser testing are illustrated.

Applicability and extrapolation model for SEE characterization using 14 MeV neutron
2016 Edition, September 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The use of 14 MeV neutron generators provides several strong advantages over spallation sources. This study aims at better defining the domain of applicability of this kind of facility for SEE characterization. Based on experiments using 14...

SEE Characterization of the New RTAX-DSP (RTAX-D) Antifuse-Based FPGA
2010 Edition, Volume 57, December 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A comprehensive SEE characterization at high-frequencies (up to 120 MHz) of the new space-flight RTAX-D antifuse-based FPGA family is presented. SEE hardening-by-design techniques in the main FPGA programmable architectures have been implemented. It is...

Poly Encapsulated LOCOS Lateral Isolation for 0.25 μm CMOS
1996 Edition, September 1, 1996 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper the feasibility of a lateral isolation scheme based on poly encapsulated LOCOS for 0.25 μm CMOS technologies is demonstrated. Excellent bird's beak dimension control is achieved with limited process complexity. The influence of field...

Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS
1993 Edition, September 1, 1993 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 μm CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer LOCOS isolation scheme....

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