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Scaled CMOS technologies with low sheet resistance at 0.06-μm gate lengths
1998 Edition, Volume 19, May 1, 1998 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance...

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the...

TSV Transistor – vertical metal gate FET inside a Through Silicon VIA
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A new vertical field-effect transistor (FET) has been fabricated inside a through silicon VIA (TSV). Front- and backside of a 200 μm thin p-doped Si wafer were highly n-doped to shape the source / drain areas of the FET. The lateral surface of the TSV forms the channel with a...

A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are co-processed and co-integrated using a gate-last process, enabling short gate-lengths (Lg=40 nm) and allowing selective digital etching of the channel. Two different common gate-stacks, including various...

Self-organized Ge nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet n-FETs featuring high ON-OFF drain current ratio
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We reported experimental fabrication and characterization of Si0.15Ge0.85 n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. This unique gate-stacking heterostructure...

Impact of Randomly Distributed Dopants on Ω-Gate Junctionless Silicon Nanowire Transistors
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents experimental and simulation analysis of an Ω-shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15...

Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and...

Increased Mobility in Enhancement Mode 4H-SiC MOSFET Using a Thin SiO2 / Al2O3 Gate Stack
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A field effect mobility of 125 cm2/V·s and a subthreshold slope of 130 mV/dec were obtained in enhancement mode 4H-SiC MOSFETs with a channel length of 2 μm. The fabricated devices utilised a gate stack comprising a 0.7 nm thin thermal SiO2, thereby reducing defects...

Superior Performance of 5 nm Gate Length GaN Nanowire nFET for Digital Logic Applications
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this work, we investigate the performance of 5 nm gate length GaN nMOS nanowire field effect transistor (GaN-NW-nFET) of various geometrical shapes, around the limits of cross sectional scalability, using atomistic quantum transport simulations. Benchmarking results...

Flexible In-Ga-Zn-O Thin-Film Transistors With Sub-300-nm Channel Lengths Defined by Two-Photon Direct Laser Writing
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, the low-temperature (≤ 150 °C) fabrication and characterization of flexible indium-gallium-zinc-oxide (IGZO) top-gate thin-film transistors (TFTs) with channel lengths down to 280 nm is presented. Such extremely short channel lengths in flexible...

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