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Reverse programmed SONOS memory technique for 0.18μm embedded utilization
2007 Edition, Volume 12, December 1, 2007 - Tsinghua University Press Ltd.

A 4 Mb embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory was developed with a 0.18 μm CMOS logic compatible technology. A reverse programming array architecture was proposed to reduce the chip area, enhance the operating window, and increase the read...

Experimental techniques on the understanding of the charge loss in a SONOS nitride-storage nonvolatile memory
2016 Edition, July 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The endurance and charge loss are the most critical issue in the design of a SONOS memory cell. The origin of the window closure and charge loss was partly caused by the electrons and holes mismatch along the channel lateral direction during the cycling. In this paper, two measurement...

Fabrication of SONOS flash memory device by using engineered tunnel barrier technique
2014 Edition, August 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Flash memory is a device that used as a tool to store data electrically without external power supply. The charge-trap such as SONOS structure is the most widely used in flash memory technology fabrication due to the advantages of this device in term of scaling and performance...

Investigation of the reliability degradation of scaled SONOS memory transistors
2015 Edition, October 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The polarity-dependent device degradation during AC stress of polysicilicon-oxide-nitride-oxide-silicon (SONOS) transistor poses considerable reliability challenges for scaled SONOS gate oxide thicknesses. However, the mechanism responsible for the endurance degradation...

A novel reverse read array architecture for embedded SONOS type flash memory
2004 Edition, Volume 1, January 1, 2004 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The reverse read characteristics of SONOS type flash memory is researched and a novel array architecture with reverse read operation is proposed in this paper. A divided common-source-line NOR architecture is adopted to realize reverse read operation which...

180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory
2006 Edition, September 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 1.8/3.3V 4Mb (512K times 8 bit) embedded SONOS flash memory has been successfully developed and verified with 180nm CMOS logic compatible integrated technology, in which a reverse programming array architecture and a novel high speed sensing circuit with...

Estimation of Trapped Charge Density in SONOS Flash Memory Using a Parallel Capacitor Model
2011 Edition, Volume 58, October 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes a model established using the parallel connection of MOS and floating-gate MOS capacitors to examine the electric properties of polysilicon-oxide-nitride-oxide-silicon (SONOS) Flash memory in both the fresh and programmed states. A linear relationship...

A Novel Channel-Program-Erase Technique with Substrate Transient Hot Carrier Injection for SONOS Memory Application
2006 Edition, September 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A novel and uniform channel program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot hole (STHH)...

A new SONOS memory using source-side injection for programming
1998 Edition, Volume 19, July 1, 1998 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in...

A Novel Ion-Bombarded and Plasma-Passivated Charge Storage Layer for SONOS-Type Nonvolatile Memory
2012 Edition, Volume 33, October 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A novel technique combination of ion bombardment (IB) and NH3 plasma treatment (PT) has been presented to yield a highly effective charge storage layer for Si/SiO2/Si3N4/SiO2/Si (SONOS)-type nonvolatile memory applications. The IB technique creates additional trap...

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