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Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS
2010 Edition, February 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Spin-torque-transfer (STT) magnetoresistive random-access memory (MRAM) [1-3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access....

A Drift-Tolerant Read/Write Scheme for Multilevel Memristor Memory
2017 Edition, Volume 16, November 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Memristor based crossbar memories are prime candidates to succeed the Flash as the mainstream nonvolatile memory due to their density, scalability, write endurance and capability of storing multibit per cell. In this paper, we present a memristor crossbar memory architecture...

Short-SET: An energy-efficient write scheme for MLC PCM
2014 Edition, August 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Phase change memory (PCM) has many advantages over the traditional DRAM technology, hence it becomes a promising candidate for main memory. Multi-level cell (MLC) PCM has the benefits of higher capacity and lower cost-per-bit due to store multiple bits in a single cell....

Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs
2015 Edition, January 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

State-of-art SRAM designs use either the negative bit line or the overdrive word line write assist circuits to improve the write-ability in a low voltage VDDMIN environment. But at the higher voltage operations, these write assist circuits will have an adverse...

A Latency-optimized and Energy-efficient Write Scheme in NVM-based Main Memory
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Non-volatile memory technologies (NVMs) are promising candidates as the next-generation main memory due to high scalability and low energy consumption. However, the performance bottlenecks, such as high write latency and low cell endurance, still exist in NVMs. To...

Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The write operation of a resistive memory based on a one-selector-one-resistor (1S1R) crossbar array consumes significant energy and is dependent on the device and circuit characteristics as well as the bias scheme. In this paper, the energy efficiency of a...

BPS: A Balanced Partial Stripe Write Scheme to Improve the Write Performance of RAID-6
2015 Edition, September 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Nowadays RAID is widely used due to its large capacity, high performance and high reliability. With the increasing requirement of reliability in storage systems and fast development of cloud computing, RAID-6, which can tolerate concurrent failures of any two disks, receives...

Write scheme for multiple Complementary Resistive Switch (CRS) cells
2014 Edition, September 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Amongst emerging technologies with the potential to usher in a new generation of Non Volatile Memory (NVM) is the memristor. The memristor makes it possible to build simple and highly dense memory structure via cross point architecture. Memristor array however suffers exponentially...

A three-stage-write scheme with flip-bit for PCM main memory
2015 Edition, January 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Phase-change memory (PCM) is a nonvolatile memory which suffers slow write performance and limited write endurance. Besides, writing a one to a PCM cell needs longer time but less electrical current than writing a zero. In traditional PCM schemes, zeros and...

Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors
2018 Edition, Volume 26, April 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The write operation of a resistive memory based on a one-selector-one-resistor (1S1R) crossbar array consumes significant energy and is dependent on the device and circuit characteristics as well as the bias scheme. In this paper, the energy efficiency of a...

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