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KronGÇôBranin Modeling of Y-Y-Tree Interconnects for the PCB Signal Integrity Analysis
2017 Edition, Volume 59, April 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The signal distribution interconnect network modeling plays an important role during the digital/mixed printed circuit board (PCB) design. With the increase of the design complexity, the PCB interconnect...

Efficient Mesh of Tree Interconnect for FPGA Architecture
2007 Edition, December 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper we present a new mesh of tree FPGA architecture, where clusters are surrounded by a mesh style interconnect and each cluster local interconnect is equivalent to a depopulated tree-based topology. The particularity of the...

Distributed model of two-level asymmetrical PCB interconnect tree
2013 Edition, September 1, 2013 - EMC Europe Foundation

A distributed behavioral model of two-level 1:n (1-input and n-outputs) asymmetrical interconnect tree network is explored. Based on circuit approach, theoretic analysis illustrating the mechanism of the underlying model extraction is...

Performance evaluation of SDN-enhanced MPI allreduce on a cluster system with fat-tree interconnect
2014 Edition, July 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Nowadays, supercomputers play an essential role in high-performance computing. In general, modern supercomuputers are built as a cluster system, which is a system of multiple computers interconnected on a network. In coding a parallel program on such a cluster system, MPI (Message Passing...

Performance Characteristics of an SDN-Enhanced Job Management System for Cluster Systems with Fat-Tree Interconnect
2014 Edition, December 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In the era of cloud computing, data centers that accommodate a series of user-requested jobs with a diversity of resource usage pattern need to have the capability of efficiently distributing resources to each user job, based on individual resource usage...

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory
2015 Edition, Volume 23, September 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In...

Repeater insertion in tree structured inductive interconnect
2001 Edition, Volume 48, May 1, 2001 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the maximum...

Repeater insertion in tree structured inductive interconnect
1999 Edition, January 1, 1999 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The effects of inductance on repeater insertion in RLC trees is the focus of the paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of possible cost functions such as minimizing the...

Analysis and application for integrity of PCB signal
2010 Edition, September 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The integrity analysis of the PCB signal has already seemed to be more important due to the use of high-speed clock, high-speed signal delivers, high definition, high-speed spare part. In the paper, signal...

Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis
2013 Edition, June 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The CMOS technology scaling has greatly improved the overall performance and density of Field Programmable Gate Array (FPGA), nonetheless the performance gap between FPGA and ASIC has remain very wide mainly due to the programmable interconnect overhead....

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