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Influence of the MOS varactor gate doping on the performance of a 2.7GHz–4GHz LC–VCO in standard digital 0.12µm CMOS technology
2002 Edition, January 1, 2002 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The influence of the gate type of the MOS varactor on the tuning range and phase noise of a fully integrated LC-VCO (voltage controlled oscillator) is presented. Three varactors in...

Analyzing the Effect of High-k Dielectric-Mediated Doping on Contact Resistance in Top-Gated Monolayer MoS₂ Transistors
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A scalable process that can yield low-resistance contacts to transition metal dichalcogenides is crucial for realizing a viable device technology from these materials. Here, we systematically examine the effect of high-k dielectric-mediated doping on...

Back-Gate Bias and Substrate Doping Influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidelines
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, we present physical insights into the role of substrate on the anomalous frequency behavior of small-signal transconductance and output conductance in the ultrathin body and buried oxide fully depleted...

Performance Evaluation and Optimization of Single Layer MoS₂ Double Gate Transistors With Schottky Barrier Contacts
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The making use of 2-D material as transistor channel is a rapid growth field since it can provide enough gate controllability for transistors at scaling limit. Among all kinds of 2-D materials, monolayer MoS₂ stands out because of its...

Simulation of 1-Nanometer Gate MoS 2 MOSFETs
2018 Edition, October 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The results of a theoretical study on the behavior of MoS 2 MOSFETs with an ultimately short gate length of 1 nm are presented. By quantum-mechanical simulations, the impact of design features such as gate...

Modeling of Hysteretic Jump Points in Ferroelectric MOS Capacitors
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Negative capacitance devices generally exhibit hysteresis, which can be exploited for memory but should be suppressed for logic devices. The significant nonlinearity of ferroelectric (FE) metal-oxide-semiconductor (MOS) capacitor makes it difficult to manipulate hysteresis,...

Back-Gate Bias and Substrate Doping Influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidelines
2019 Edition, Volume 66, February 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, we present physical insights into the role of substrate on the anomalous frequency behavior of small-signal transconductance and output conductance in the ultrathin body and buried oxide fully depleted...

Ultrafast and Low-Turn-OFF Loss Lateral IEGT With a MOS-Controlled Shorted Anode
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A novel ultrafast and low-loss lateral injection-enhanced gate transistor (LIEGT) is proposed and investigated by simulation. The device features a MOS-controlled shorted anode (MCSA) and a bias voltage (VAG) applied between the anode trench...

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SiₓGe₁₋ₓ and InₓGa₁₋ₓAs: Part II-Fits and Extraction From Experimental Data
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Capacitance-voltage (C-V) measurement and analysis is highly useful for determining important information about MOS gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage, fixed oxide charge, density of...

Online Contextual Influence Maximization with Costly Observations
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In the Online Contextual Influence Maximization Problem with Costly Observations, the learner faces a series of epochs in each of which a different influence spread process takes place over a network. At the...

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