loading
In-situ epitaxial silicon—oxide-doped polysilicon structures for MOS field-effect transistors
1986 Edition, Volume 7, October 1, 1986 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Limited reaction processing (LRP) has been used to achieve the in-situ growth of epitaxial silicon-oxide-doped polysilicon layers. The in-situ growth of these multiple layers was combined with the selective epitaxial growth...

IIIB-3 Limited reaction processing: In-situ epitaxial silicon thin-oxide polysilicon layers for MOS transistors
1986 Edition, Volume 33, November 1, 1986 - IEEE - Institute of Electrical and Electronics Engineers, Inc.
A description is not available for this item.
In situ-doped epitaxial silicon film growth at 250 degrees C by an ultra-clean low-energy bias sputtering
1989 Edition, January 1, 1989 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The use of ultraclean technology to produce a dramatic reduction in the processing temperature has been demonstrated for silicon epitaxy by low-energy bias sputtering. Damage-free in situ substrate surface cleaning by extremely low-energy Ar ion bombardment has...

Electrical characterization of junctions and bipolar transistors formed with in situ doped low-temperature (800 degrees C) epitaxial silicon
1991 Edition, Volume 38, January 1, 1991 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The results of characterization of junctions and bipolar transistors formed with in situ doped low-temperature (800 degrees C) epitaxial silicon are presented. The epitaxial silicon layers were deposited by ultra-low pressure chemical vapor...

Fabrication and characterization of bipolar transistors with in-situ doped low-temperature (800 degrees C) epitaxial silicon
1989 Edition, Volume 10, August 1, 1989 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The authors report the fabrication of bipolar transistors at a maximum process temperature of 800 degrees C, utilizing in situ doped low-temperature epitaxial silicon deposited by ultralow-pressure chemical vapor deposition (U-LPCVD), and their subsequent...

Correspondence between MOS and modulation-doped structures
1984 Edition, Volume 31, March 1, 1984 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Arguments are presented clearly establishing the physical correspondence between metal-oxide-semiconductor (MOS) and metal/ AlGaAs/GaAs modulation-doped structures. Direct use of MOS formalism in modeling the modulation-doped...

Selective Epitaxial Germanium Growth on Silicon - Trench Fill and In Situ Doping
2012 Edition, June 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Single-crystal germanium (Ge) offers high electron and hole mobilities and is a viable candidate for channel materials in advanced metal-oxide-semiconductor field-effect transistors (MOSFETs). This work encompasses heteroepitaxial Ge growth on...

25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)
2011 Edition, Volume 58, May 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor (MOS). In this paper, a carbon-doped Si (Si:C) layer under an undoped Si layer is...

A high-performance directly insertable self-aligned ultra-rad-hard and enhanced isolation field-oxide technology for gigahertz silicon NMOS/CMOS VLSI
1989 Edition, Volume 36, April 1, 1989 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The authors describe a novel field-oxide structure for rad-hard NMOS/CMOS VLSI. This is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD...

In situ cleaning of silicon wafers for selective epitaxial growth (SEG)
1990 Edition, September 1, 1990 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The effects of pre-bake temperature, pressure and duration have been studied for silicon SEG substrates. Silicon cusp and trough formation adjacent to the oxide sidewalls in association with the undercutting of the oxide features is reported. Activation...

Advertisement