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Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS
1993 Edition, September 1, 1993 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 μm CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer...

An Optimized Poly-Buffered LOCOS Process for a 0.35 μm CMOS Technology
1994 Edition, September 1, 1994 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

For a 0.35 μm CMOS technology, an optimized poly buffered LOCOS process is necessary in order to meet the design rules. In this paper, the feasibility of this isolation scheme is demonstrated.

Poly Encapsulated LOCOS Lateral Isolation for 0.25 μm CMOS
1996 Edition, September 1, 1996 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper the feasibility of a lateral isolation scheme based on poly encapsulated LOCOS for 0.25 μm CMOS technologies is demonstrated. Excellent bird's beak dimension control is achieved with limited process complexity. The influence of field oxide...

SEE characterization of the AMS 0.35 μm CMOS technology
2013 Edition, September 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents experimental results for the single-event effects characterization of a commercial (Austria Microsystems) 0.35 μm CMOS technology. It improves and expands previous results. The knowledge gained is being applied in the development of a RHBD digital...

Miniature 0.25-μm CMOS distributed amplifier using on-chip inductors
2010 Edition, July 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A CMOS distributed amplifier incorporating on-chip patterned ground shield (PGS) spiral inductors has been developed using a standard low-cost 0.25-μm CMOS process. Measured results show that this distributed amplifier has an average gain of 7 dB, return loss of more than 10...

0.5 μm CMOS Device Design and Characterization
1987 Edition, September 1, 1987 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n+ polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control...

Device Characterisation of a High-Performance 0.25 μm CMOS Technology
1992 Edition, September 1, 1992 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 μm CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects were...

4 Gbit/s Driver/Multiplexer in 0.8 μm CMOS
1996 Edition, September 1, 1996 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A low-swing high-speed differential CMOS output-driver/multiplexer is presented. A testchip, designed in a standard 0.8 μm CMOS process, has performed 4 Gbit/s multiplexing of a 16-bit fixed-pattern. Design and measurements of this testchip are presented

22 GHz amplifier using a 0.12 μm CMOS technology
2006 Edition, May 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 22 GHz low-noise amplifier (LNA) was designed, fabricated in standard 0.12 μm CMOS technology and measured. The LNA chip achieves a maximum gain of 5.5 dB, a noise figure of 10.3 dB and return losses at in-/output of 15 and 10 dB, respectively. The LNA operates at a supply...

Advanced Ti Salicide Process for Sub-0.2 μm CMOS
1996 Edition, September 1, 1996 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that...

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