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Notice of Removal: FPGA Logic Block to Implement Resource-Efficient Multiplexers
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Removed.

Digit-serial reconfigurable FPGA logic block architecture
1998 Edition, January 1, 1998 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a novel field-programmable gate array logic block architecture which incorporates support for digit-serial DSP architectures on a digit-wide basis, without diminishing the support for random and control logic applications. To efficiently...

A flexible multiplication unit for an FPGA logic block
2001 Edition, Volume 4, January 1, 2001 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

FPGAs are increasingly being applied to DSP applications but are often inefficient in space and time compared with dedicated DSP chips, particularly for multiplication-based operations. To improve FPGA arithmetic performance, a flexible multiplication unit and...

Online Fault Tolerance for FPGA Logic Blocks
2007 Edition, Volume 15, February 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate...

Analysis of FPGA Logic Block Architectures and Functional Improvement of Fine Grained Cells
2006 Edition, Volume 4, June 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Up to date, many different FPGA logic block architectures, varying in size, functionality and complexity, have been proposed. The most common FPGA logic blocks either have multiplexers or look-up-tables (LUTs). This article evaluates the...

BIST-based diagnostics of FPGA logic blocks
1997 Edition, January 1, 1997 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance. In this paper we present the first approach able to diagnose faulty programmable logic blocks...

Algebra-logical repair method for FPGA logic blocks
2010 Edition, September 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An algebra-logical repair method for FPGA functional logic blocks on the basis of solving the coverage problem is proposed. It is focused on implementation into Infrastructure IP for system-on-a chip and system-in-package. A method is designed for providing the...

An approach for detecting multiple faulty FPGA logic blocks
2000 Edition, Volume 49, January 1, 2000 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An approach is proposed to test FPGA logic blocks, including part of the configuration memories used to control them. The proposed AND tree and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test...

Pattern-based FPGA logic block and clustering algorithm
2014 Edition, September 1, 2014 - Technical University of Munich (TUM)

In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering...

How much logic should go in an FPGA logic block
1998 Edition, Volume 15, January 1, 1998 - IEEE Computer Society

The logic blocks of most FPGAs contain clusters of lookup tables and flip-flops yet little is known about good choices for key parameters. How many lookup tables should a cluster contain, how should FPGA routing flexibility change as cluster size changes, and how many...

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