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Design and fabrication of p-channel FET for 1-µm CMOS technology
1982 Edition, January 1, 1982 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A retrograde n-well is shown to be good for 1-µm bulk CMOS technology using n+polysilicon gates. P-Channel FET's with a threshold voltage of -0.6V fabricated in a retrograde n-well show small short-channel threshold lowering and good...

A 0.5 mu m CMOS/SOI technology
1991 Edition, January 1, 1991 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The authors describe a 0.5- mu m fully depleted CMOS technology built on thin SIMOX (separation by implanted oxygen) substrates using an accumulation mode device design for both n- and p-channel FETs. The 0.5- mu m...

Quantum well p-channel AlGaAs/InGaAs/GaAs devices for complementary heterostructure FET applications
1988 Edition, Volume 35, December 1, 1988 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The low extrinsic transconductance of the p-channel self-aligned gate heterostructure insulated gate FETs (HIGFETs), resulting from low hole mobility and high source resistance, has limited the performance of these devices. Results are presented for...

1.0-µm n-well CMOS/bipolar technology
1985 Edition, Volume 32, February 1, 1985 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

High-performance 1.0-µm n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously...

Fabrication and simulation of vertical Ge-based P-channel planar-doped barrier FETs with 40 nm channel length
2017 Edition, October 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Ge integrated on Si is a promising candidate for energy-efficient field effect transistor (FET) applications due to its high mobility and compatibility to CMOS technology. Nevertheless, using Ge in FET fabrication is challenging due to difficulties...

Process and device performance of 1 µm-channel n-well CMOS technology
1984 Edition, Volume 31, February 1, 1984 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The process and device performance of 1 µm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω.cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging...

N- and p-well process compatibility in a 1µm-CMOS technology
1984 Edition, January 1, 1984 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 1 µm CMOS concept for 5 V supply-voltage with 22 nm gate oxide and a pure TaSi 2 gate is presented which allows to realize a n-well- and a p-well-process with widely compatible process flow. Starting in either case from 20 Ωcm epitaxial material on 0.02...

A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy
1985 Edition, Volume 32, February 1, 1985 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p+substrate and a retrograde n-well. Self-aligned TiSi 2 is formed on n+and p+diffusions to reduce the sheet resistance and...

Silicon on Depletion Layer FET (SODEL FET) for sub-50 nm high performance CMOS applications: novel channel and S/D profile engineering schemes by selective Si epitaxial growth technology
2002 Edition, January 1, 2002 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, novel channel & S/D profile engineering schemes are proposed for sub-50 nm bulk CMOS applications. These devices, referred to as "Silicon On DEpletion Layer (SODEL) FETs", have the depletion layer beneath the channel region, which works as an...

A 1M SRAM with full CMOS cells fabricated in a 0.7µm technology
1987 Edition, January 1, 1987 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification...

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