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A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step
2013 Edition, Volume 48, December 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor...

An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC
2015 Edition, July 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

High speed analog to digital converters (ADC), memory sense amplifiers, RFID applications, data receivers with low power and area efficient designs has attracted a wide variety of dynamic comparators. This paper presents an improved design for a...

Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC
2011 Edition, November 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A digital-domain calibration is proposed for a split-capacitor DAC of a 0.5 V 11 bit 10 kS/s differential-type SAR ADC. The calibration improves the linearity of ADC, especially INL by +1.59/-1.71 LSB, SFDR by 19.1 dB, and SNDR by 5.0 dB (ENOB...

A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window
2018 Edition, May 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 0.35 V 100 kS/s 10-bit successive approximation register (SAR) ADC with adaptive window (AW) in 90 nm CMOS. The SAR ADC uses the transient information of the latch comparator to create redundancy ranges....

A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a 12-bit 1-kS/s successive approximation register analog-to-digital converter (ADC) is presented for biomedical signal processing system. A multi-segmentation digital-to-analog converter architecture and a hybrid switching scheme are proposed to...

An ultra-low power interface CMOS IC design for biosensor applications
2012 Edition, August 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a design example of an ultra-low power single-channel analog front-end (AFE) integrated circuits (IC) and system for biomedical sensing applications. The 0.18-µm CMOS AFE IC design includes a low noise instrumentation amplifier (INA), a...

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents an 11-bit ultralow voltage energy efficient successive approximation register (SAR) analog-to-digital converter (ADC). With the proposed semi-resting (SR) digital-to-analog convertor (DAC) switching scheme, this paper consumes only 6%-13.5%...

A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS
2016 Edition, Volume 63, March 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is...

A 1-V 8-bit 0.95mW successive approximation ADC for biosignal acquisition systems
2009 Edition, May 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a 1-V 8-bit 10 kS/s successive approximation (SA) analog-to-digital converter (ADC) with ultra-low power characteristic is implemented for biosignal acquisition systems. To decrease power consumption, a passive sample-and-hold...

A 0.9 V low-power reconfigurable successive approximation ADC for integrated sensors
2013 Edition, June 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a reconfigurable successive approximation analog-to-digital converter with selectable resolutions ranging from 7 to 10 bits is presented. The circuit is implemented in IBM CMOS 0.13 μm technology, and operates with a 0.9 V supply. The simulated...

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