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A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing
2010 Edition, Volume 57, January 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 10-MS/s-to-100-kS/s power-scalable fully differential comparator-based switched-capacitor (CBSC) 10-bit pipelined analog-to-digital converter (ADC) is presented. To operate over a wide range of sampling rates, an adaptive biasing technique...

Design and Implementation of a Rail-to-Rail 460-kS/s 10-bit SAR ADC for the Power-Efficient Capacitance Measurement
2015 Edition, Volume 64, April 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents the design and implementation of a rail-to-rail 460-kS/s 10-bit successive approximation register analog-to-digital converter (ADC) for the power-efficient capacitance measurement. The specifications of ADC are optimized at system...

8 - An American National Standard IEEE Standard for Mechanical Core Specifications for Microcomputers
1988 Edition, January 1, 1988 - IEEE - Institute of Electrical and Electronics Engineers, Inc.
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A subthreshold 8-bit 78.4nw 17.8 kS/s 0.18um SAR ADC for RFID sensing applications
2011 Edition, May 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Summary from only given. In this paper an ultra low power SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power...

A subthreshold 8-bit 78.4nw 17.8 kS/s 0.18um SAR ADC for RFID sensing applications
2011 Edition, May 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper an ultra low power SAR ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power comparator with...

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface
2011 Edition, Volume 46, March 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The...

A subthreshold ultra low power 22fJ/conversion Flash ADC for RFID sensing applications
2011 Edition, May 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper an ultra low power Flash ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power Track-and-Latch comparator...

A subthreshold ultra low power 22fJ/conversion flash ADC for RFID sensing applications
2011 Edition, May 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper an ultra low power Flash ADC for RFID application is presented. Several techniques are used to further reduce the power consumption and relatively elevate the speed of the ADC. These techniques include a low power Track-and-Latch comparator...

An ultra low power 10-bit 1KS SAR-ADC for ECG signal recording applications
2016 Edition, March 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 10-bit 1 kS/s SAR ADC in 0.13μm CMOS technology for ECG signal recording applications. Two new techniques are introduced:1) a novel DAC switching method designed for fully-differential SAR ADC...

The Design and Optimization of a 25 kS/s 10 bit Micropower Current S/H Cell for Weak Current Bio-medical Applications
2008 Edition, January 1, 2008 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a micropower current sample-and-hold front-end is designed for weak current bio-medical applications in a 0.35-mum standard CMOS process. The design reduces the distortion of the current-mode sample-and-hold stage by exploiting the exponential I-V relationship of...

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