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An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications
2018 Edition, Volume 65, January 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an...

An 11-bit 250-nW 10-kS/s SAR ADC with doubled input range for biomedical applications
2017 Edition, August 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching...

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications
2012 Edition, Volume 47, November 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion...

A 10-bit 110 kS/s 1.16 $\mu\hbox{W}$ SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications
2014 Edition, Volume 61, August 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 10-bit 110-kS/s successive-approximation analog-to-digital converter (ADC) for multichannel biomedical applications is presented. In order to achieve low-power operation, the ADC utilizes a reduced-speed dynamic comparator, a low-complexity...

A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC
2018 Edition, Volume 65, November 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant...

A 7.6-nW 1-kS/s 10-bit SAR ADC for Biomedical Applications
2019 Edition, November 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 10-bit successive approximation register analogue-to-digital converter with energy-efficient switching scheme for biomedical applications. The energy-efficient switching scheme achieves an average digital-to-analog converter switching...

A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window
2014 Edition, June 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V...

A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications
2009 Edition, November 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. Splitting comparator and energy saving capacitor array are proposed to achieve low power consumption. The average switching energy of the...

A 6.38 fJ/conversion 0.6V 0.43++W 100 kS/s 10-bit successive approximation ADC
2016 Edition, May 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents a 10-bit successive approximation ADC for low voltage and low power applications. The chip operating voltage is 0.6 V with single-ended rail-to-rail swing input signal. Binary-weighted multilayer sandwich capacitor array is used in the...

Design of a rail-to-rail 460 kS/s 10-bit SAR ADC for capacitive sensor interface
2013 Edition, December 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 460 kS/s 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with rail-to-rail input range is proposed for acquiring capacitive sensor. The specifications of ADC are optimized at system level, emphasizing...

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