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An 8-bit 10 kS/s 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities
2007 Edition, November 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An 25-muW 1.8V 8-bit 10 kS/s successive approximation (SAR) analog to digital converter (ADC) was designed and fabricated in a 0.18 mum CMOS technology for passive UHF RFID applications. The resistive digital to...

A 43-nW 10-bit 1-kS/s SAR ADC in 180nm CMOS for biomedical applications
2015 Edition, November 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents an ultra-low power 10-bit, 1-KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. To achieve the nano-watt range power consumption, an ultra-low-power...

A low power 10-bit 300 kS/s RSD coded pipeline A/D-converter
1996 Edition, January 1, 1996 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-/spl mu/m CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure...

A 10-Bit 200-kS/s 1.76-μW SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less...

A 10-bit 200-kS/s 1.76-μW SAR ADC with Hybrid CAP-MOS DAC for Energy-Limited Applications
2018 Edition, May 27, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power and area efficient 10-bit SAR ADC with hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC, which consumes less power and much smaller chip area than a pure CDAC. Instead of...

An ultra-low-power 10-Bit 100-kS/s successive-approximation analog-to-digital converter
2009 Edition, May 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Successive-approximation analog-to-digital converters (SA-ADCs) have recently been widely used for moderate-speed moderate-resolution applications where power consumption is of major concern. In this paper, several techniques are proposed to further reduce the power consumption...

A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications
2016 Edition, Volume 63, April 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes a fully differential 10-bit energy efficient successive approximation register (SAR) analog-to-digital converter (ADC) by using incremental converting method. The voltage difference of the input between two successive samples is acquired and resolved....

An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an...

A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching
2016 Edition, Volume 63, December 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-voltage and power-efficient 10 bit successive-approximation register (SAR) analog-to-digital converter (ADC). The input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive digital-to-analog...

A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant...

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