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A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter
2011 Edition, Volume 46, November 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a wide-bandwidth, low-noise 4 GHz All-Digital PLL. It uses a rotary traveling wave oscillator (RTWO) as the oscillator core. By using multiphase signals available from the RTWO, the analog phase information is directly converted into the...

A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC
2010 Edition, Volume 45, December 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A digital PLL (DPLL) with a time-to-digital converter (TDC) embedded within a digitally controlled oscillator (DCO) has been implemented in 65 nm CMOS occupying an active area of 0.027 mm . The quantization step of the TDC...

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise
2015 Edition, November 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a fractional-N digital PLL achieving low in-band phase noise. The phase detection is carried out by a proposed 10-bit, 0.8 ps resolution TDC using a charge pump and a SAR-ADC, with low power and small...

An all-digital PLL with SAR frequency locking system in 65nm SOTB CMOS
2016 Edition, October 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents an all-digital PLL (ADPLL) which synthesizes any frequency using the successive approximation (SAR) algorithm. The proposed ADPLL consists of a high-frequency resolution digitally controlled oscillator, a time-to-digital converter,...

A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter
2006 Edition, September 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low in-band phase noise. The TDC uses a novel architecture that combines...

A low power all-digital PLL with power optimized digitally controlled oscillator
2010 Edition, December 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about...

A 0.0043-mm² 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a synthesized fractional-N digital phase-locked loop (PLL) with a speculative dual-referenced interpolating time-to-digital converter (DI-TDC). The DI-TDC measures a fractional phase by...

A compact 6 GHz to 12 GHz digital PLL with coupled dual-LC tank DCO
2010 Edition, June 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A digital PLL, realized in 45nm SOI CMOS, features a dual LC-tank DCO with nested inductors, achieving an octave of tuning range and area of 0.111 mm2. Digital control of coupled LC-tanks creates new capabilities, enabling a 10% increase in tuning...

A novel digital PLL with good performance and very small area
2011 Edition, December 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A novel digital PLL(Phase Locked Loop) is presented in this paper. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and cycle control to digitally control the DCO(Digitally Controlled...

A 0.0043-mm2 0.3–1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC
2019 Edition, Volume 54, January 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a synthesized fractional-N digital phase-locked loop (PLL) with a speculative dual-referenced interpolating time-to-digital converter (DI-TDC). The DI-TDC measures a fractional phase by...

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