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A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
2016 Edition, Volume 51, February 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and...

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8- $\mu$ s Settling Time for Multi-ISM-Band ULP Radios
2019 Edition, Volume 66, September 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes a wideband ultra-fast-settling fractional-N bang-bang digital phase-locked loop (DPLL) for multi-ISM-band ultra-low-power (ULP) radios. We propose a mismatch-free digital-to-time-converter (DTC) gain calibration scheme to effectively...

A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
2010 Edition, Volume 45, November 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 0.3-1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The ALGC reduces the nonlinearity of the bang-bang phase-frequency...

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2.5-5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs)...

A 3.5–6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise
2016 Edition, September 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range...

A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection
2018 Edition, Volume 65, September 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2.5-5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs)...

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection
2015 Edition, September 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a low-phase-noise subharmonically injection-locked all-digital phase-locked loop (PLL) with simplified overall architecture based on a complementary switched injection technique and a sub-sampling bang-bang detector (SSBBPD) is...

A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery
2006 Edition, September 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a digital PLL for low long-term jitter clock recovery. A jitter reduction scheme for digitally controlled oscillator is proposed and 39% jitter reduction is observed. A 5-phase digital phase frequency detector (PFD) has 265 ps...

A low-cost, leakage-insensitive semi-digital PLL with linear phase detection and FIR-embedded digital frequency acquisition
2010 Edition, November 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A semi-digital PLL utilizing a hybrid DCO is presented. A mixed-mode loop control with an analog proportional path and a digital integration path provides linear phase tracking, leakage-insensitive loop filtering, and technology scalability....

A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation
2011 Edition, Volume 46, March 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase...

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