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All-Digital PLL with Ultra Fast Acquisition
2005 Edition, November 1, 2005 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A fully-digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally-controlled oscillator that deliberately avoids any analog tuning controls. The conventional phase/frequency detector, charge pump and RC loop...

A digital PLL with finite impulse responses
1995 Edition, Volume 1, January 1, 1995 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Conventional phase-locked loops (PLLs) lack speed, because ordinary phase comparators cannot provide time-continuous operation thus they act as a time delay to cause instability. In contrast, a completely time-discrete scheme, with a special voltage-controlled...

A CMOS digital PLL with improved locking
2004 Edition, Volume 2, January 1, 2004 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector (DPFD) is presented. The self-calibration technique is employed to acquire fast acquisition, low-jitter and wide frequency range. The DPLL works from 60 to 600 MHz with a...

A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise
2017 Edition, Volume 52, July 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel...

A Digital PLL with a Stochastic Time-to-Digital Converter
2006 Edition, January 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip...

A Digital PLL With a Stochastic Time-to-Digital Converter
2009 Edition, Volume 56, August 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits...

A 4 GHz fractional-N frequency synthesizer
2000 Edition, Volume 1, January 1, 2000 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 4 GHz fractional-N frequency synthesizer for telecommunications applications is presented. The synthesizer includes a multiple-modulus ECL prescaler capable of operating at input frequencies of up to 4.3 GHz with a power dissipation of 17.6...

FPGA-based programmable digital PLL with very high frequency resolution
2011 Edition, December 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A FPGA-based tunable all-digital control system featuring high resolution all-digital PLL is presented. The whole system has been designed under Simulink environment and synthesized with QuartusII. The system can achieve very high frequency resolution (0.1Hz)...

A High-Resolution 2-GHz Fractional-N PLL With Crystal Oscillator PVT-Insensitive Feedback Control
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This letter presents a 2-GHz fractional-N phase-locked loop (PLL) with a high-precision delta-sigma digital-to-analog converter (DAC) to overcome the frequency deviation of a crystal oscillator due to manufacturing process,...

A novel all-digital PLL with software adaptive filter
2004 Edition, Volume 39, March 1, 2004 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The phase-locked loop (PLL) is one of the key building blocks of modern electronic designs. This paper presents a novel PLL structure that utilizes a "flying-adder" frequency synthesizer as its digital control oscillator (DCO), a software implemented...

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