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A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Realizing the vision of a trillion IoT sensor nodes demands ultra low-power (ULP) compute, typically implemented using synchronous digital systems. These require low-power clock sources which must be fully integrated to meet low system-cost requirements. Hence, relaxation oscillators (RxOs)...

Analysis of screening effects in multiple-gate and gate-all-around Si NW array FETs
2017 Edition, September 1, 2017 - Japan Society of Applied Physics - JSAP

The performance of Silicon nanowire (NW) FETs with multiple parallel cylinderical channels can significantly be affected by screening effects depending on the gate structure. This work analyzes electrostatic screening effects in single gate (SG) and double gate (DG) structures and compares the...

A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch...

An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling...

An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A fully integrated CMOS temperature-to-digital converter utilizing MOSFETs in the sub-threshold region is proposed. The temperature-to-digital converter achieves the ultra-low power operation required for Internet of Things (IoT) nodes. The proposed principle takes the ratio of the...

Novel GAA Si Nanowire p-MOSFETs with Excellent Short Channel Effect Immunity via an Advanced Forming Process
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional HKMG FinFET flow are implemented to fabricate the GAA...

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-μm CMOS
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) for bio-potential signal acquisition: skip-reset, delta (Δ) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme...

NW-TFET analog performance for different Ge source compositions
2013 Edition, October 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower...

A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic
2018 Edition, January 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a sub-10 nW bandgap reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit was implemented with a 0.18μm CMOS process and generates voltage and current references of 1.238 V and 6.64 nA while consuming 9.3 nW....

A 0.4-V 0.93-nW/kHz Relaxation Oscillator Exploiting Comparator Temperature-Dependent Delay to Achieve 94-ppm/°C Stability
2018 Edition, Volume 53, October 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents the analysis and design of a relaxation oscillator that counteracts the complementary-toabsolute-temperature (CTAT) property of the comparator delay with the proportional-to-absolute-temperature (PTAT) property of the RC core to realize temperature-stabilized operation....

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