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Circuit of an EEPROM sense amplifier in 0.18 µm CMOS technology
2011 Edition, November 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A sense amplifier for EEPROM memory competent of functioning under a very low-voltage power supply is presented. The sense amplifier was designed for an EEPROM realized with a 0.18-µm CMOS technology. Key design techniques of power...

Silicon lateral avalanche photodiodes fabricated by standard 0.18 µm CMOS process
2009 Edition, September 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A Si APD was fabricated by standard 0.18 µm CMOS process. The maximum avalanche gain was 224 for only 8 V bias. The bandwidth was 1.6 GHz for low avalanche gain and 800 MHz for large avalanche gain.

Low-power high-linearity 0.13-µm CMOS WCDMA receiver front-end
2010 Edition, December 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power high-linearity variable gain WCDMA receiver (Rx) front-end. The Rx front-end consists of a variable gain low noise amplifier (LNA) and a folded double balanced mixer. By enhancing the...

0.13-µm CMOS load modulator for MIMO system
2016 Edition, August 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents load modulator based on the six-port modulator. To allow arbitrary load impedances to be used, a new circuit architecture with a technique to design the high resolution impedance is proposed and implemented. A theoretical model of the proposed modulator is...

A high-Psat high-PAE fully-integrated 5.8-GHz power amplifier in 0.18-µm CMOS
2011 Edition, November 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 5.8-GHz 0.18-µm CMOS fully integrated power amplifier (PA) with high saturated output power (Psat), high output 1-dB compressed point (O P1dB ), and high power-added efficiency (PAE) is presented in this paper. This PA consists of two stages, the...

Fully integrated high efficiency K-band PA in 0.18 µm CMOS technology
2009 Edition, November 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A fully integrated 2 stage K-band power amplifier is designed, fabricated and measured. The amplifier is realized utilizing standard 0.18 µm CMOS process. A novel simplified matching and bias network is used in order to reduce the input and output losses...

An Analog Front-End Circuit for CO 2 Sensor Readout in 0.18-µm CMOS Process
2019 Edition, April 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An analog front-end (AFE) trans-impedance amplifier (TIA) for CO 2 detector is presented. It senses the current generated from the IR detector, which contains the information of the CO 2 concentration in the air. An automatic IR sensor baseline current calibration loop is proposed to cancel...

A MEMS variable capacitor with piezoresistive position sensing fabricated in a standard 0.35 µm CMOS process
2010 Edition, May 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A variable MEMS capacitor with piezoresistive feedback is presented. The capacitor is fabricated in a commercial 0.35 µm CMOS process with MEMS post-processing. The work presented demonstrates a piezoresistive sensing scheme capable of controlling hysteresis...

Integrated micro-solar cell structures for harvesting supplied microsystems in 0.35-µm CMOS technology
2009 Edition, October 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper we present a solar harvester test chip, realized to characterize several integrated solar cell structures, gathering the information required to design a complete power management system for handling the harvested energy. In particular, we realized photodiodes...

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS
2010 Edition, September 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A laser-diode (LD) driver with interwoven mutually-coupled peaking inductors for high-speed optical networks is presented. Six and four inductors are interwoven into two sets of inductors for area-effective implementation as well as performance enhancement. The proposed circuit is fabricated...

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