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A Type-I Sub-Sampling PLL With a 100 x 100 μm² Footprint and -255-dB FOM
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A dual-loop LC-voltage-controlled oscillator (VCO)-based frequency synthesizer, composed of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, sub-sampling phase-locked loop (SS-PLL), is presented. A compact SS...

A Type-I Sub-Sampling PLL With a $100\times100\,\,\mu\text{m}^{2}$ Footprint and255-dB FOM
2018 Edition, Volume 53, December 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A dual-loop LC -voltage-controlled oscillator (VCO)-based frequency synthesizer, composed of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, sub-sampling phase-locked loop (SS-PLL), is presented. A compact SS...

A 0.008mm2 2.4GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a −239.7dB FoM and −64dBc reference spurs
2018 Edition, April 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A ring-oscillator (RO) based PLL is presented combining a type-I architecture and a sub-sampling phase detector (SSPD). It achieves low jitter thanks to the wide-bandwidth type-I loop and low reference spurs thanks...

Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a feedforward phase noise cancellation technique to reduce phase noise of the output clock signal of a phase-locked loop (PLL). It uses a sub-sampling phase detector to measure the phase noise and a variable time delay for...

30.8 A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fs rms Integrated Jitter and -256.4dB FoM
2019 Edition, February 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Lowering supply voltage is an effective way to reduce circuit power consumption, especially in digital-centric system-on-chips (SoC). For low-jitter phase-locked loops (PLL) required in high-speed serial links and data converters, operation under low voltage is highly desirable such...

A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Despite their inherent stability, area-efficient loop filters, and insensitivity to phase-frequency detector nonlinearity and dead-zone, type-I phase-locked loops (PLLs) are used infrequently because of two major limitations--limited lock-range and large...

A 0.01mm2 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with −254dB FOM
2018 Edition, February 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Power consumption, Performance in terms of phase noise and integrated jitter, and Area (PPA) are three design metrics that have driven countless research efforts in CMOS frequency-synthesizer design. Design limitations and system-level tradeoffs have made simultaneous...

A 2 GHz 3.1 mW type-I digital ring-based PLL
2016 Edition, September 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a type-I digital ring-based PLL with wide loop bandwidth to lower the ring oscillator's noise contribution. The in-band noise is addressed using a SAR-ADC-based sampling phase detector (SPD). A stacked reference buffer is...

A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter
2019 Edition, Volume 66, January 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Despite their inherent stability, area-efficient loop filters, and insensitivity to phase-frequency detector nonlinearity and dead-zone, type-I phase-locked loops (PLLs) are used infrequently because of two major limitations-limited lock-range and large...

A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-locked clock multipliers have demonstrated some of the lowest jitters for a given power consumption (jitter-power FoMj metric). However, they contain a tradeoff between...

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