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A low power 12-bit and 30-MS/s pipeline analog to digital converter in 0.35μm CMOS
2008 Edition, June 1, 2008 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital...

A low power 25 MS/S 12-bit pipelined analog to digital converter for wireless applications
2003 Edition, January 1, 2003 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 12 bit 25 MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.35 /spl mu/m CMOS technology. The proposed new high speed class AB opamp makes it possible to achieve...

A 12-bit — 35-MS/s pipeline ADC with dynamic element matching correction for ILC/CALICE integrated read-out
2009 Edition, October 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A low power 12 bits analog to digital converter is a critical part of a fully integrated readout system for the next ILC ECAL. We present here a new design of 12-bit ADC up to...

A 12 Bit Direct Level-Signal Transition Based Pipelined Analog-to-Digital Converter
2007 Edition, December 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 12-bit 100-MS/s pipelined analog-to-digital converter designed in a 0.18-μm CMOS process. Unlike conventional pipelined analog-to-digital converters,...

A 13 bit 20 Ms/s current mode pipelined analog to digital converter
1999 Edition, January 1, 1999 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A pipelined analog to digital converter based on open loop differential CMOS switched current amplifiers is presented. It is hard to meet the requirements of opamps for conventional switched capacitor ADCs at low power...

A 13 bit 20 Ms/s current mode pipelined analog to digital converter
1999 Edition, Volume 1, January 1, 1999 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A pipelined analog to digital converter based on open loop differential CMOS switched current amplifiers is presented. For high accuracy, conventional ADCs require fast, high gain amplifiers and high quality double poly capacitors that are not...

A 12-bit 50MS/s Low-Power Pipeline ADC for WiMAX
2010 Edition, Volume 1, March 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a 12-bit 50-MS/s pipeline analog-to-digital converter(ADC) is presented. A digital-adjustable bias current generator scales the opamp bias currents. By this means, the power consumption...

A 22mW 10-bit 150-MS/s pipelined ADC in 1.2V 65nm CMOS
2010 Edition, November 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents the low-power implementation of a 10-bit 150-MS/s pipelined analog-to-digital converter (ADC) in a standard 65 nm digital CMOS. The ADC removes the track-and-hold...

A new 12-b 40 ms/s, low-power, low-area pipeline ADC for video analog front ends
2005 Edition, January 1, 2005 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 12-bit, 40 MS/s pipelined analog-to-digital converter (ADC) is designed in 0.18-/spl mu/m CMOS technology with 1.8 V single power supply. The proposed ADC architecture uses a combination of...

A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS
2011 Edition, November 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 12-bit 100-MS/s pipeline analog-to-digital converter (ADC) in a 45-nm CMOS technology. The low-voltage circuit techniques and a careful layout are adopted to...

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