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A Digital PLL Based 2nd-Order ΔBandpass Time-Interleaved ADC
2018 Edition, August 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a time-interleaved (TI) VCObased band-pass ADC with a second-order bandstop noise transfer function. The proposed ADC uses a digital phase-locked loop (PLL) based architecture and employs current...

Digital PLL-based adaptive repetitive control
2006 Edition, January 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The repetitive control achieves zero steady state error by reducing it in iterations based on the error observed in pervious iterations. However, the repetitive control requires that an integer number of samples of the input periodic signal are taken and this could be a problem when...

A digital-PLL-based true random number generator
2005 Edition, Volume 1, January 1, 2005 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A true random number generator (RNG) based on a digital phase-locked loop (PLL) has been designed and implemented in a 1.5/spl mu/m CMOS process. It achieved an output data rate of 100 kbps from the sampling of two 30MHz ring oscillators, and successfully...

A performance comparison of 16 QAM digital PLL based demodulators
1994 Edition, January 1, 1994 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A quantitative assessment of acquisition performance and a unified comparison of all the proposed carrier synchronization structures for QAM is missing from the literature. This paper is an attempt to provide that analysis and performance comparison. It presents statistical...

A performance analysis of a digital PLL based MPSK demodulator
1995 Edition, Volume 43, February 1, 1995 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a generalized nonlinear (Markov) analysis technique that is used to evaluate the statistical performance of uniformly sampled digital phase-locked loop (DPLL) demodulators. This paper characterizes the first-order, decision-directed DPLL based...

A Markov Analysis of Digital PLL Based Mpsk Demodulators
1993 Edition, January 1, 1993 - IEEE - Institute of Electrical and Electronics Engineers, Inc.
A description is not available for this item.
A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS
2011 Edition, June 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as...

A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
2012 Edition, May 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents the design of a digital PLL which uses a high resolution Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter (TDC) for low noise RF application. The TDC uses two gated ring oscillators (GRO) acting as the delay lines in...

A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter
2012 Edition, May 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents the design and the implementation of a low power bang-bang all digital phase locked loop (BBADPLL). The design of the proposed architecture is based on the programmable coefficients of the digital loop filter (DLF) that manages the tradeoffs between...

A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS
2014 Edition, June 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We propose a new architecture of an all-digital PLL (ADPLL) for advanced cellular radios that is optimized for 28 nm CMOS. It is based on a wide tuning range, fine-resolution class-F DCO with only switchable metal capacitors and a phase-predictive TDC. The...

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