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A continuous-time, jitter insensitive ΣΔ modulator using a digitally linearized G m -C integrator with embedded SC feedback DAC
2011 Edition, June 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper explores the use of a digitally linearized, low-power G m -C integrator in the first stage of a 5th order continuous time sigma-delta modulator. The proposed architecture features a jitter...

Jitter compensation technique for continuous-time sigma-delta modulator
2014 Edition, November 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter:...

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We combine a first-order single-bit CTΔΣM employing finite impulse-response (FIR) feedback with a 1-bit second-order ΔΣ back end to achieve a modulator with maximum stable amplitude (MSA) that is close to full scale, and a third-order overall...

A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 4-bit, third-order, continuous-time ΣΔ modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented...

Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively...

Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The use of a single-bit quantizer in a wideband \CTDSM is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit \CTDSMS are plagued by a host of difficulties. Clock jitter and quantizer metastability are...

A $\Sigma \Delta$ -FIR-DAC for Multi-Bit $\Sigma \Delta$ Modulators
2013 Edition, Volume 60, September 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a new digital-to-analog converter (DAC) is proposed for multi-bit continuous-time sigma-delta modulators (ΣΔMs). This -finite-impulse-response-DAC (ΣΔ-FIR-DAC) digitally converts the multi-bit output of the...

Colored clock jitter model in audio continuous-time ΣΔ modulators
2015 Edition, June 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper the effect of colored clock jitter on audio continuous-time ΣΔ modulators is studied. The results demonstrate the importance of using the correct model for the jitter on the clock signal, especially when it is generated by a...

A gm/ID Methodology Based Data-Driven Search Algorithm For the Design of Multi-Stage Multi-Path Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents a methodology for sizing transistors of a multi-stage, multi-path capacitor-less feed-forward compensated operational amplifiers employed in advanced CMOS process implementation of continuous-time bandpass ΣΔ-modulators. The paper...

Active-RC continuous-time DSM with FIR+SCR DAC
2017 Edition, October 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB...

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