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A clock tuning circuit for system–on–chip
2002 Edition, January 1, 2002 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Clock distribution in System-on-Chip (SoC) designs has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an on-chip clock tuning...

A clock-tuning circuit for system-on-chip
2003 Edition, Volume 11, August 1, 2003 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

System-on-chip (SoC) design depends heavily on effective reuse of semiconductor intellectual property (IP). Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock...

In-circuit self-tuning of clock latencies
2005 Edition, January 1, 2005 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Random manufacturing variations and changes in operating conditions can alter the relative timing of data and clock signals and cause timing violations. Increasing relative magnitude of manufacturing variations and accommodating a wide range of operating conditions necessitate large...

On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging
2012 Edition, Volume 31, December 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Lifetime performance of digital integrated circuits degrades as a consequence of circuit aging. In the past few years, there has been extensive research to reduce the impact of aging by different design techniques, or to predict the degradation and adapt the circuit...

Measurement of a clock-tuned digital non-Foster circuit for positive or negative digital capacitance
2017 Edition, March 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Theory and measured results are presented for a clock-tuned digital capacitor that provides digital implementation of a variable non-Foster negative capacitance or a variable positive capacitance. Unlike previous digital non-Foster capacitor designs, the...

Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements
2015 Edition, Volume 34, November 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Post-silicon clock tuning elements are widely used in high-performance designs to mitigate the effects of process variations and aging. Located on clock paths to flip-flops, these tuning elements can be configured through the scan chain so that clock skews...

Automatic Tuning Circuit for Gm-C Filters
2005 Edition, December 1, 2005 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a CMOS on-chip automatic tuning circuit using phase lock loop (PLL) technique for continuous-time Gm-C filters. In the tuning circuit, to achieve the maximum tuning accuracy, the new VCO architecture that generates...

In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation
2011 Edition, November 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Addressing lifetime performance degradation caused by circuit ageing has been a topic of active research for the past few years. In this paper we present a different perspective to this problem, by leveraging the presence of clock tuning elements that are...

A low-power microcontroller with on-chip self-tuning digital clock-generator for variable-load applications
1999 Edition, January 1, 1999 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Clock disabling for power management has been implemented in some microcontrollers, but the wake-up time of Xtal/PLL-based systems is incompatible with fast interrupt response. On the other hand, hardwired on-chip clocking has been used for...

Hardware Assisted Clock Synchronization for Real-Time Sensor Networks
2013 Edition, December 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Time synchronization in wireless sensor networks is important for event ordering and efficient communication scheduling. In this paper, we introduce an external hardwarebased clock tuning circuit that can be used to improve synchronization and significantly reduce...

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