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A 6-GS/s 6-bit time interleaved SAR-ADC
2013 Edition, October 1, 2013 - European Microwave Association

This paper presents a 6-GS/s 6-bit time-interleaved successive approximation register (SAR) analog to digital converter (ADC) realized in 90-nm CMOS. The ADC consists of 32 single SAR-ADCs. The measured...

A 6-GS/s, 6-bit, at-speed testable ADC and DAC pair in 0.13µm CMOS
2009 Edition, April 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper demonstrates a 6-GS/s 6-bit flash ADC and current-steering DAC pair in 0.13µm CMOS. Averaging and interpolating techniques are applied to reduce the offsets and to save the power of the...

A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications
2013 Edition, Volume 48, December 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents the design of a 40-nm CMOS 10.3-GS/s 6-bit Flash ADC used as the analog frontend of a universal DSP-based receiver that meets the requirements for all the NRZ 10G Ethernet (10GE) standards, for both fiber and copper...

A hybrid 3 Gs/s, 6-bit digital to analog converter
1989 Edition, January 1, 1989 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A hybrid GaAs 3-gigasample-per-second (Gs/s) digital-to-analog converter (DAC) is presented. Five-bit 1-Gs/s operation and peak operating speeds of 3 Gs/s are demonstrated. DC differential and integral linearity are...

A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing
2010 Edition, Volume 45, August 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks...

A 2-GS/s 6-bit flash ADC with offset calibration
2008 Edition, November 1, 2008 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-mum CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed...

A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS
2014 Edition, Volume 61, July 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This brief presents an improved timing scheme for a 4× interleaved 6-bit pipelined binary search (PLBS) analog-to-digital converter (ADC). The individual channel consists of a calibrated fully dynamic PLBS architecture with a 1-bit folding front-end....

A 60-GS/s 6-Bit DAC in 0.5-µm InP HBT Technology for Optical Communications Systems
2011 Edition, October 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 60-GS/s 6-bit digital-to-analog converter (DAC) for beyond-100-Gb/s/ch optical communications systems. The DAC was designed and fabricated using our in-house 0.5-μm InP HBT technology, which yields a...

A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS
2009 Edition, September 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An asynchronous 6bit 1GS/s ADC is achieved by time interleaving two ADCs based on binary successive approximation algorithm (SA) using a capacitive ladder. The semi-close loop asynchronous technique eliminates the high internal clocks and significantly...

A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM
2015 Edition, September 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An area-efficient time-domain conversion technique is reported to achieve 10-GS/s, 6-bit resolution in 65-nm CMOS. The front-end single voltage-to-time converter (VTC) running at full speed obviates any clock-skew calibration often needed...

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