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A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS
2007 Edition, September 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A digitally calibrated 8-bit folding ADC incorporating redundancy and reassignment is described. Small, redundant folder and comparator circuits generate 1024 available zero-crossings. An entirely self-contained calibration engine selects 255 zero-crossings from...

A 50MS/s 80dB SFDR digital calibrated pipelined ADC with workload-balanced MDAC
2011 Edition, November 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A workload-balanced multiplying digital-to-analog converter (WB-MDAC) is proposed to improve the settling efficiency of multi-bit pipeline stages, and demonstrated in a 14-bit 50-MS/s digital calibrated pipelined ADC. The presented...

Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC
2013 Edition, October 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 14-bit and 200-MS/s SHA-less pipelined ADC is implemented by 0.13 μm CMOS process with blind least mean square (BLMS) calibration technique which corrects errors of this pipelined ADC with fast, low gain and inaccurate opamps. Using skip and fill...

A successive-approximation-register ADC architecture for digital background calibration in high speed ADCs
2014 Edition, October 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a digital background calibration scheme using an 8-b 10-MS/s successive approximation register (SAR) ADC to calibrate an 8-b 100-MS/s pipelined folding ADC is presented. In order to sample high...

A 0.9 V 9 mW 1MSPS digitally calibrated ADC with 75 dB SFDR
2003 Edition, January 1, 2003 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A low-voltage two-stage algorithmic ADC incorporating the Opamp-Reset Switching Technique (ORST) is presented. The low-voltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switched-opamp. The ADC employs...

An 8-bit 30 MS/s 18 mW ADC with 1.8 V single power supply
2001 Edition, January 1, 2001 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes an 8-bit 30 MS/s 18 mW ADC (Analog-to-Digital Converter) with 1.8 V single power supply for battery powered systems. A folding and interpolation architecture with the auto-zeroed amplifiers is newly developed to achieve the low...

A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 μm CMOS
2007 Edition, May 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero...

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR
2008 Edition, Volume 55, November 1, 2008 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current-voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured...

A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR
2010 Edition, September 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A digital calibration scheme is proposed to reduce the power consumption in a switched-capacitor (SC) ΔΣ ADC. When opamp bias current is reduced in the integrators, nonlinear settling errors dominate the output spectrum, causing harmonic distortion. The...

A 281-nW 43.3 fJ/conversion-step 8-ENOB 25-kS/s asynchronous SAR ADC in 65nm CMOS for biomedical applications
2013 Edition, May 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes a low-power 25-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The ADC employs a novel low-energy and area-efficient tri-level switching scheme in the DAC. Compared to...

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