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A 550- $\mu\hbox{W}$ 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction
2011 Edition, Volume 46, August 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three...

A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction
2010 Edition, September 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A speed-enhanced 10b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented in this paper. Three virtually divided sub-DACs have a 0.5 LSB over-range between stages owing to...

A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A low-power pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) using boosted bucket-brigade device (BBD) for residue charge processing is presented. Boosted BBDs have been used as low-power and high-precision residue charge transfers in...

A 0.003 mm $^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching
2015 Edition, Volume 50, June 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes a single-channel, calibration-free Successive-Approximation-Register (SAR) ADC with a resolution of 10 bits at 240 MS/s. A DAC switching technique and an addition-only digital error correction...

A 10 bit 5 MS/s column SAR ADC with digital error correction for CMOS image sensors
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes a SAR ADC whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the...

A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement
2017 Edition, August 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for...

A 6-bit 0.81-mW 700-MS/s SAR ADC With Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 6-bit high-speed successive approximation register analog-to-digital converter (ADC) with sparkle-code correction. By quantizing the comparator decision time (CDT), the sparkle codes are identified and corrected, reducing the error...

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a fully synthesizable successive-approximation-register (SAR) analogto- digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using...

A 6-bit 0.81-mW 700-MS/s SAR ADC With Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration
2018 Edition, Volume 53, March 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 6-bit high-speed successive approximation register analog-to-digital converter (ADC) with sparkle-code correction. By quantizing the comparator decision time (CDT), the sparkle codes are identified and corrected, reducing the error...

An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers
2013 Edition, Volume 60, September 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 12-bit 3-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) was implemented with a modified addition-only digital error correction (ADEC) and a dual-register-based DAC control as...

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