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A 48-dB DR 80-MHz BW 8.88-GS/s bandpass ΔΣ ADC for RF digitization with integrated PLL and polyphase decimation filter in 40nm CMOS
2011 Edition, June 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2.22GHz 4th-order BP ΔΣ ADC has been realized in 40nm CMOS. The test chip contains a complete system consisting of the ADC core, the PLL with clock generation network, and the digital decimation filters and...

A 6.1 GS/s 52.8 mW 43 dB DR 80 MHz bandwidth 2.4 GHz RF bandpass ΔΣ ADC in 40 nm CMOS
2010 Edition, May 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2.4 GHz 4th order BP ΔΣ ADC is presented. The feedforward topology uses Gm-LC resonators that can be calibrated in frequency. The quantizer is split in 6 interleaved comparators to relax speed. Clocked at 6.1 GHz, it achieves a DR of 43 dB...

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass $\Delta\Sigma$ Modulator and Polyphase Decimation Filter
2012 Edition, Volume 47, April 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A fourth-order continuous-time RF bandpass ΔΣ ADC has been fabricated in 40 nm CMOS for fs/4 operation around a 2.22 GHz central frequency. A complete system has been implemented on the test chip including the ADC core, the...

A Dynamic Zoom ADC With 109-dB DR for Audio Applications
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the...

A 0.6 V 74.2 dB-DR Continuous-Time Sigma-Delta Modulator with Inverter-Based Amplifiers
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This brief presents a 0.6 V third-order continuous-time sigma-delta modulator (CT-SDM) based on single-stage inverter-based amplifiers. The designed amplifier uses an on-chip bulk-bias technique to control the common mode output voltage and to mitigate process, voltage and...

A 106.7-dB DR, 390-μW CT 3rd-order ΣΔ modulator for MEMS microphones
2015 Edition, September 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 3rd-order continuous-time ΣΔ modulator for MEMS microphones in 0.16-μm CMOS technology achieves 106.7-dB DR and 93.2-dB peak SNDR, consuming 390 μW from a 1.6-V power supply and occupying an area of 0.21 mm2. The ΣΔ modulator,...

Supply-terminal 40 MHz BW characterization of impedance-like nonlinear functions for envelope tracking PAs
2016 Edition, May 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We present an approach for the dynamic characterization of the non-idealities arising in envelope tracking (ET) systems when either the radio-frequency (RF) power amplifier (PA) or the supply modulator (SM) are driven into nonlinear operation. Impedance-like nonlinear...

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC
2009 Edition, Volume 44, October 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required....

A 0.6-V, 74.2-dB DR Continuous-Time Sigma–Delta Modulator With Inverter-Based Amplifiers
2018 Edition, Volume 65, October 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This brief presents a 0.6 V third-order continuous-time sigma-delta modulator (CT-SDM) based on single-stage inverter-based amplifiers. The designed amplifier uses an on-chip bulk-bias technique to control the common mode output voltage and to mitigate process, voltage and...

A 2 mW, 50 dB DR, 10 MHz BW 5 $\times$ Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF
2015 Edition, Volume 62, January 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma (ΔΣ) modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a...

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