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A 42 mW 2 GS/s 4-bit flash ADC in 0.18-μm CMOS
2009 Edition, November 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A low power 4-bit 2 GS/s flash ADC is presented. To enhance the speed, the analog part of the ADC is fully pipelined; reset switches are inserted into preamplifiers and comparators for fast overdrive recovery. Post-simulation results...

A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS
2007 Edition, September 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A compact 5-bit flash ADC is designed and fabricated in TSMC 0.13-μm CMOS process. Resistive averaging network and interpolation are discussed and analyzed for power reduction. This proposed ADC consumes 180 mW from a 1.2 V...

A 4 GS/s, 1.8 V multiplexer encoder based flash ADC using TIQ technique
2014 Edition, February 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Analog-to-Digital converters (ADC) are useful components in signal processing and communication systems. In the digital signal processing (DSP) low power and low voltage are of prime concern and it is challenging to design high speed mixed signal circuits. This paper describes...

A 3 bit 20 GS/s flash ADC in 65 nm low power CMOS technology
2010 Edition, September 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 20 GS/s 3 bit flash ADC with a wide analog bandwidth is realized in a 65 nm CMOS technology. By employing a fourfold parallelization a high sampling rate is achieved, while a large input bandwidth is...

A 5-bit 1-GS/s Flash-ADC in 0.13-μm CMOS Using Active Interpolation
2006 Edition, September 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents a 5-bit 1-GS/s flash-ADC in 0.13-μm CMOS technology. An active interpolation topology is used in the comparator inputs to reduce power consumption and input capacitance of the converter. Operating at 1...

A 40 GS/s 4 bit SiGe BiCMOS flash ADC
2017 Edition, October 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents the design and experimental test of a 40 GS/s 4 bit single-core flash ADC in a 0.13 μm SiGe BiCMOS technology. The ADC exploits a traveling-wave concept and integrates a new low-complexity...

CMOS ADCs Towards 100 GS/s and Beyond
2016 Edition, October 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The implementation of a 64x time-interleaved ADC in 32nm CMOS SOI is analyzed. Measurement results confirm 33 dB SNDR up to 19.9 GHz at 90 GS/s and 1.2V supply. Architecture details and analysis show insights into limitations and potentials of the chosen...

A 6-bit 1.6 GS/s Flash ADC in 0.18-μm CMOS with Reversed-Reference Dummy
2006 Edition, November 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 6-bit 1.6 GS/s CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The...

A 40 GS/s SiGe track-and-hold amplifier
2008 Edition, October 1, 2008 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

An ultra-high-speed SiGe track-and-hold amplifier (THA) using a switched-emitter-follower (SEF) configuration is presented. Operating off a +5.5 V power supply, this THA exhibits -32.4 dBc of total harmonic distortion (THD) when sampling a 10 GHz input signal at the rate of 40...

A 6-GS/s 6-bit time interleaved SAR-ADC
2013 Edition, October 1, 2013 - European Microwave Association

This paper presents a 6-GS/s 6-bit time-interleaved successive approximation register (SAR) analog to digital converter (ADC) realized in 90-nm CMOS. The ADC consists of 32 single SAR-ADCs. The measured effective-number-of-bits...

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