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A 280 μW Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the...

A 280 $\mu$ W Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW
2018 Edition, Volume 53, December 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the...

A 15.2-ENOB 5-kHz BW 4.5-μW Chopped CT ΔΣ-ADC for Artifact-Tolerant Neural Recording Front Ends
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Implantable closed-loop neural stimulation is desirable for clinical translation and basic neuroscience research. Neural stimulation generates large artifacts at the recording sites, which saturate existing recording front ends. This paper presents a low-power continuous-time...

A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus...

An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS
2016 Edition, Volume 51, December 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The successive-approximation-register (SAR) architecture is well known for its high power efficiency in medium-resolution analog-to-digital converters (ADCs). However, when considered for high-precision applications, SAR ADCs suffer from non-linearity resulting from capacitor...

A Continuous-Time Zoom ADC for Low-Power Audio Applications
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta-sigma modulator (CTDSM). Compared...

A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces
2014 Edition, September 1, 2014 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A two-step incremental ADC (IADC) is proposed for low-bandwidth, micro-power sensor interface circuits. This architecture extends the order of a conventional IADC from N to (2N-1) by using a two-step operation, while requiring only the circuitry of an Nth-order...

A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection
2013 Edition, Volume 7, August 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes a low-power configurable neural recording system capable of capturing and digitizing both neural action-potential (AP) and fast-ripple (FR) signals. It demonstrates the functionality of epileptic seizure detection through FR recording. This system features...

A 1-V 175-μW 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both...

A 1 V 175 μW 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques
2018 Edition, April 1, 2018 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2-1 MASH switched-capacitor delta-sigma modulator was fabricated using a 65 nm CMOS technology. We constantly alternate the circuit configurations of its internal integrators to optimize power consumption. The integrators are accelerated only when they are in crucial...

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