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A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping $\Delta\Sigma$ TDC
2012 Edition, Volume 47, April 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a low-power noise-shaping ΔΣ time-to-digital converter (TDC) and its application to a fractional-N digital PLL. With a simple structure of single-delay-stage Δ modulator followed by a...

A 2 GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC
2011 Edition, June 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2 GHz fractional-N digital PLL with a single delay cell, noise shaping ΔΣ TDC is implemented in a 0.13µm CMOS. With a simple structure of Δ modulator followed by a charge pump...

A 2.8–3.2-GHz Fractional- $N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO
2013 Edition, Volume 48, March 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 2.8-3.2-GHz fractional-N digital PLL, implemented in 0.18- μm CMOS, is presented. The PLL architecture has the form of a classic delta-sigma fractional-N PLL. A PFD generates up and down pulses from...

A 1.9-GHz Fractional-N Digital PLL With Subexponent $ \Delta\Sigma$ TDC and IIR-Based Noise Cancellation
2012 Edition, Volume 59, November 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent ΔΣ time-to-digital converter (TDC) and an infinite impulse response (IIR)-based noise cancellation scheme. The proposed subexponent ΔΣ...

A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- ${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power
2011 Edition, Volume 46, December 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-time converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider...

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques
2009 Edition, Volume 44, March 1, 2009 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them...

A 1.75 mW 1.1 GHz Semi-Digital Fractional-N PLL With TDC-Less Hybrid Loop Control
2012 Edition, Volume 22, December 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 1.1 GHz semi-digital fractional-N PLL without the time-to-digital converter (TDC) whose resolution and linearity heavily depends on process and temperature variations is implemented in 65 nm CMOS. A hybrid loop control with...

A High-Resolution 2-GHz Fractional-N PLL With Crystal Oscillator PVT-Insensitive Feedback Control
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This letter presents a 2-GHz fractional-N phase-locked loop (PLL) with a high-precision delta-sigma digital-to-analog converter (DAC) to overcome the frequency deviation of a crystal oscillator due to manufacturing...

A CMOS digital PLL with improved locking
2004 Edition, Volume 2, January 1, 2004 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector (DPFD) is presented. The self-calibration technique is employed to acquire fast acquisition, low-jitter and wide frequency range. The DPLL works from 60 to 600 MHz with a...

A 0.12-mm² 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-μs Settling Time for Multi-ISM-Band ULP Radios
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes a wideband ultra-fast-settling fractional-N bang-bang digital phase-locked loop (DPLL) for multi-ISM-band ultra-low-power (ULP) radios. We propose a mismatch-free digital-to-time-converter (DTC) gain calibration scheme to effectively...

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