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A 14-bit, 40-MS/s DAC with current mode deglitcher
2002 Edition, Volume 1, January 1, 2002 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 14-bit current steering DAC utilizing a current mode track-and-hold circuit as a deglitcher is presented. The deglitcher is based on a developed highly linear current memory. The prototype circuit is designed in a 0.35-/spl mu/m BiCMOS (SiGe)...

A 12-bit 1.74-mW 20-MS/s DAC with resistor-string and current-steering hybrid architecture
2015 Edition, September 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a novel segmented hybrid digital-to-analog converter (DAC). It uses a resistor-string as the LSB part for low-power consumption, and uses a current-steering array as the MSB part for high-speed and small size. The LSB and MSB parts are combined...

A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a Nyquist-rate current-steering digital-to-analog converter that achieves a peak spurious-free dynamic range better than 87 dB and a peak signal-to-noise-and-distortion ratio better than 77 dB over a 265-MHz signal band. It is enabled by...

A 10-b, 300-MS/s power DAC with 6-V pp differential swing
2013 Edition, June 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 10-bit digital-to-analog converter (DAC) is presented that delivers 6-Vpp into a 100-Ω differential load. The circuit is implemented in 45-nm CMOS SOI, which provides benefits for using a FET-stack current buffer. The measured DNL is better than 0...

A 14-b 150 MS/s CMOS DAC with Digital Background Calibration
2006 Edition, January 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 14-b 150MS/s current-steering DAC with background calibration technique is demonstrated. Digital background calibration loop trims the static performance less than plusmn 0.55 LSB. The DAC achieves the spurious free dynamic range (SFDR) of 81dB at 1.6MHz...

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping
2011 Edition, Volume 46, June 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q...

An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture
2008 Edition, May 1, 2008 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents an 8 bit 1.8 V 500 MSPS digital- to analog converter using 0.18mum double poly five metal CMOS technology for frequency domain applications. The proposed DAC is composed of four unit cell matrix. A novel decoding logic is used to remove the...

A 10-bit 400-MS/s current-steering DAC with process calibration
2013 Edition, September 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 10-bit 400-MS/s current-steering DAC is proposed in this paper. A proposed process detector, and a current calibration circuit are used in the binary current cells to calibrate the current error due to the process variation. Besides,...

A 14-bit 100 MS/s self-calibrated DAC with a randomized calibration-period
2010 Edition, November 1, 2010 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background self-calibration technique with a randomized calibration-period is adopted to improve the dynamic performance. The DAC is fabricated in...

A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Successive approximation register (SAR) analog-to-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area....

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