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A 100 MHz Current Conveyor in 0.35 μm CMOS Technology
2007 Edition, November 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper a new 0.35 μm CMOS technology second generation current conveyor (CCII) is presented. It is a low power (60 μA @ ± 1.5 V power supply) circuit, featuring 88 +ù 100 μm2 area, 100 MHz bandwidth and 10 GHz...

SEE characterization of the AMS 0.35 μm CMOS technology
2013 Edition, September 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents experimental results for the single-event effects characterization of a commercial (Austria Microsystems) 0.35 μm CMOS technology. It improves and expands previous results. The knowledge gained is being applied in the development of a...

Device Characterisation of a High-Performance 0.25 μm CMOS Technology
1992 Edition, September 1, 1992 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 μm CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects...

22 GHz amplifier using a 0.12 μm CMOS technology
2006 Edition, May 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 22 GHz low-noise amplifier (LNA) was designed, fabricated in standard 0.12 μm CMOS technology and measured. The LNA chip achieves a maximum gain of 5.5 dB, a noise figure of 10.3 dB and return losses at in-/output of 15 and 10 dB,...

Millimeter-wave static frequency divider in 0.13-μm CMOS technology
2011 Edition, June 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Frequency dividers are one of the most significant blocks in Millimeter-wave communication systems and became a research hotspot in recent years. In this paper, an 8:1 static divider is implemented in 0.13-μm CMOS technology. The realized...

A 0.35 μm CMOS Technology Optimized for Low-Power Applications
1994 Edition, September 1, 1994 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A high performance 0.35 μm CMOS technology is presented for low operating voltages. The increased reliability margin at low supply voltages was used to scale the gate oxide thickness and optimize the channel and source/drain junctions profiles. The resulting well...

40-Gb/s Transimpedance Amplifier in 0.18-μm CMOS Technology
2006 Edition, September 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-μm CMOS technology. From the measured S-parameters, a transimpedance gain of 51.0 dBΩ and a 3-dB bandwidth up to 30.5 GHz (~0.5 fT) were observed. To the best of authors' knowledge, the TIA...

Design of 2.4 GHz differential low noise amplifier using 0.18 μm CMOS technology
2016 Edition, April 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper the inductive degenerated Differential Low Noise Amplifier (DLNA) is designed with operating frequency 2.4 GHz using 0.18 μm CMOS Technology. The DLNA is biased at 1.8 V supply and perfectly matched with input impedance of 50 Ω. Designed DLNA provides power...

Modeling of AC-DC converter using 0.18 μm CMOS technology
2012 Edition, December 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes a modeling of low-power CMOS transistors, which are suitable for AC-DC converter applications. First section described DC analysis of input and output device of CMOS transistor using Spectre simulation tool from Cadence Design Systems. After that, advanced...

An Optimized Poly-Buffered LOCOS Process for a 0.35 μm CMOS Technology
1994 Edition, September 1, 1994 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

For a 0.35 μm CMOS technology, an optimized poly buffered LOCOS process is necessary in order to meet the design rules. In this paper, the feasibility of this isolation scheme is demonstrated.

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