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1.5GSPS 4-bit flash ADC using 0.18μm CMOS
2007 Edition, December 1, 2007 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

One channel of 4 bit high speed flash ADC using a 0.18μm CMOS technology is reported. This is part of 4 channel time interleaving ADC. The design is preceded by a differential S&H circuit which operates on 1.5 GS/s. This system is suitable for...

A 0.5 V, 420 MSps, 7-bit flash ADC using all-digital time-domain delay interpolation
2012 Edition, December 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents a 0.5 V ultra-low-voltage flash ADC using an all-digital time-domain delay interpolation technique for resolution enhancement. The developed 7-bit flash ADC is implemented in a 90 nm CMOS process. By using two-way...

Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing
2017 Edition, July 1, 2017 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper proposes the different way of designing standard-cell based flash ADC in order to increase its input dynamic range. It includes implementation of 5-bit flash ADC for fully automated digital synthesis. The input dynamic range is increased by including...

An effective 6-bit flash ADC using low power CMOS technology
2013 Edition, September 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In present day communication technology, Digital communication plays a tremendous role in effective power utilization of resources. In many aspects of Digital communication, both wired and wireless communication technologies are covered. To implement a digital communication system, Analog to...

A Ku-Band 8-Element Phased-Array Receiver in O.18-μm CMOS Technology
2018 Edition, November 1, 2018 - Institute of Electronics, Information and Communication Engineers, The (IEIC)

A 15-18 GHz 8-element phased-array receiver for wireless application is presented in this paper. Each element includes a low noise amplifier (LNA), a 5-bit passive phase shifter, a 4-bit attenuator. Two pre-amplifiers are applied to compensate the insertion loss of the passive...

Design of 4 bit flash ADC using TMCC & NOR ROM encoder in 90nm CMOS technology
2015 Edition, December 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents design of 4 Bit Flash Analog to Digital Converter using a latest comparator for voltage comparison called Threshold Modified Comparator Circuit (TMCC) and NOR ROM encoder in cadence environment using 90nm CMOS Technology. The TMCC...

Comparative study of comparator and encoder in a 4-bit Flash ADC using 0.18μm CMOS technology
2012 Edition, December 1, 2012 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes a comparative study of comparator and encoder in 4-bit Flash Analog to Digital Converter (ADC) for Pipeline ADC to obtain a high speed ADC. In this paper, the conventional comparator is replaced with an open loop comparator and the...

Design and implementation of 4 bit Flash ADC using low power low offset dynamic comparator
2015 Edition, January 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.
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Corrections to "A novel distributed amplifier with high gain, low noise, and high output power in 18-μm cmos technology" [Apr 13 1533-1542]
2013 Edition, Volume 61, July 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

There is an error in the order of the references [18] and [19] in the above-named article [ibid., vol. 61, no. 4, pp. 1533-1542, Apr. 2013]. The order of these references should be exchanged. The corrected order (and numbering) of these two references are shown as follows: [18] J. Kim and J....

An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices
2019 Edition, January 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Recent studies have indicated that multilogic circuits in VLSI design helps in reducing the transistor count of circuits and increases the data transfer rate significantly. This paper presents an efficient design methodology for the implementation of a two bit ternary output Flash...

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