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0.5 μm CMOS Device Design and Characterization
1987 Edition, September 1, 1987 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n+ polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned...

0.5 μm CMOS Devices and Circuit Characterization
1989 Edition, September 1, 1989 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

CMOS circuits with feature sizes scaled down to 0.5μm [1],[2] and even less [3],[4] have already been reported. In this paper, we report the fabrication of half micron CMOS using mixed e-beam/optical lithography and Rapid Thermal Annealing (RTA) for both BPSG reflow...

Scaling Gate Electrode Thickness for 0.18 μm CMOS Devices
1994 Edition, September 1, 1994 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The thickness of a silicided, phosphorous doped, n+ polysilicon gate electrode was varied, 220nm versus 140nm, to determine its impact on device scaling and performance. CMOS devices with physical gate lengths down to 0.15μm were fabricated utilizing a twin well, double...

Technology and Device Design Constraints for Low Voltage-Low Power Sub-0.1 μm CMOS Devices
1993 Edition, September 1, 1993 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The device structure and the device design methodology to achieve the low voltage-low power sub-0.1 μm MOS devices are discussed. It is shown in the simulation that it is difficult to simultaneously satisfy two requirements to suppress the short channel...

Impact of 24-GeV proton irradiation on 0.13-μm CMOS devices
2005 Edition, September 1, 2005 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We studied the response of a commercial 0.13-μm CMOS technology to high-energy (24-GeV) proton irradiation, which emulated the environment the front-end electronics of future high energy accelerators will have to operate in, for fluences up to 1016 p/cm2. After irradiation, large...

Selective CVD TiSi 2 for Sub-0.5 μm N+/P+ CMOS Devices
1993 Edition, September 1, 1993 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We have used a new selective CVD TiSi2 in an advanced CMOS process. Subhalf-micron transistors have been characterised, with results equivalent to devices made with more conventional salicide. Ring oscillators with typical gate delay times have been fabricated. Finally, fully...

Dependence of Layout Parameters on CDE (Cable Discharge Event) Robustness of CMOS Devices in a 0.25-μm Salicided CMOS Process
2006 Edition, March 1, 2006 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of cable discharge event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been...

A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices
2011 Edition, September 1, 2011 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper describes an ultra-low-power SAR ADC in 0.13-μm CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques,...

Device Characterisation of a High-Performance 0.25 μm CMOS Technology
1992 Edition, September 1, 1992 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 μm CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of...

A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-μm 5-V CMOS Process
2013 Edition, Volume 34, May 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Based on good electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) device is used for on-chip ESD protection. The major concern of SCR is the latch-up issue, because of its low holding voltage. Previous papers tried to design latchup-immune SCR devices;...

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