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0.4-µm gate-length devices fabricated by contrast-enhanced lithography
1983 Edition, Volume 4, September 1, 1983 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process....

Nitride-based devices fabricated by wet etching
2003 Edition, January 1, 2003 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Photo-enhanced chemical (PEC) wet etching technology was used to etch GaN and AlGaN epitaxial layers. Figure 1 shows PEC etch rate for the GaN and Al/sub x/Ga/sub 1-x/N epitaxial layers in aqueous KOH and H/sub 3/PO/sub 4/ solutions. It was found that the maximum etch rates were 510...

Submicrometer Silicon MOSFET's fabricated using focused ion-beam lithography
1986 Edition, Volume 33, February 1, 1986 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Submicrometer n-channel enhancement-mode silicon MOSFET's with polysilicon gate lengths as small as 0.35 µm were fabricated using focused-ion-beam lithography. The polysilicon gate was patterned by a 80-kV Au-Si ion beam using a negative polystyrene...

A high-performance 0.25- mu m CMOS technology. II. Technology
1992 Edition, Volume 39, April 1, 1992 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

For Pt. I, see ibid., vol.39, no.4, pp.959-966 (1992). The key technology elements and their integration into a high-performance, selectively scaled, 0.25- mu m CMOS technology are presented. Dual poly gates are fabricated using a process where the poly and source/drain...

A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography
1991 Edition, January 1, 1991 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Summary form only given. A novel 0.1- mu m-gate elevated source and drain MOSFET was fabricated utilizing phase-shifted lithography. Phase-shifted lithography enabled less than 0.2- mu m spacing, resulting in a 0.1- mu m gate length in...

Characteristics of GaAs/AlGaAs HEMT's fabricated by X-ray lithography
1996 Edition, Volume 43, January 1, 1996 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper is about the dc and microwave characterization of the first high electron mobility transistors (HEMT's) realized using X-ray lithography processing. This full field patterning technology is proposed as a way to produce transistors with sub-200 nm gate lengths and...

Size effects in E-beam fabricated MOS devices
1977 Edition, January 1, 1977 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

The physical limitations imposed by geometric effects have been investigated on silicon MOS structures. N-channel silicon gate MOS transistors were fabricated using electron-beam lithography and dry-processing techniques. The devices fabricated include...

Enhanced resolution for future fabrication
2003 Edition, Volume 19, January 1, 2003 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We have developed resolution-enhanced optical lithography processes that have enabled us to fabricate devices with deep sub-100 nm feature sizes. Isolated gate features were resolved down to 40 nm in resist using optimized phase-shift lithography processes....

The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length
1999 Edition, January 1, 1999 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We have fabricated and demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET. This is the first MOSFET ever built that combines (1) a gate length controlled precisely through a deposited film thickness, independently of lithography and...

Transistor operations in 30-nm-gate-length EJ-MOSFETs
1997 Edition, January 1, 1997 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Discusses fabrication of electrically variable shallow junction MOSFETs (EJ-MOSFETs) to investigate transistor characteristics in ultra-fine gate MOSFETs. By using electron beam (EB) lithography and an ultra-high resolution resist (Calixarene), we could achieve a gate...

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