loading
0.15 µm Channel-length MOSFETs fabricated using e-beam lithography
1982 Edition, January 1, 1982 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We have fabricated MOSFETs with channel lengths as short as 0.1 µm by a modified NMOS process. The devices have been designed according to parameters obtained from numerical simulation. Electron-beam lithography has been used to define patterns at...

0.15 µm Channel-length MOSFET's fabricated using e-beam lithography
1982 Edition, Volume 3, December 1, 1982 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We have fabricated MOSFET's with channel lengths as short as 0.1 µm by a modified NMOS process. The devices have been designed according to parameters obtained from numerical simulation. Electron-beam lithography has been used to define patterns at all...

Size effects in E-beam fabricated MOS devices
1979 Edition, Volume 14, April 1, 1979 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

N-channel silicon gate MOS devices were fabricated using electron-beam lithography and dry-processing techniques. The devices fabricated include discrete transistors, inverters, and ring oscillators. Channel length and width dimensions were...

Coulomb blockade phenomena in low-dimensional Si MOSFETs fabricated using focused-ion beam implantation
1999 Edition, January 1, 1999 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We have investigated Coulomb blockade phenomena in low-dimensional Si metal-oxide-semiconductor field-effect-transistors (MOSFETs) with the very small length and very narrow width of channel regions, which are fabricated using e-beam...

Experimental technology and characterization of self-aligned 0.1µm-gate-length low-temperature operation NMOS devices
1987 Edition, January 1, 1987 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Results are presented from work aimed at demonstrating the feasibility of a Si FET technology in the 0.1µm gate length regime. Self-aligned, n-channel polysilicon gated MOSFETs were designed for optimum operation at cryogenic temperatures (77°K) with reduced power-supply levels...

Radiation effects of e-beam fabricated submicron NMOS transistors
1982 Edition, Volume 3, January 1, 1982 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper reports radiation effects of submicron NMOS devices fabricated by e-beam lithography. This study was initiated because e-beam lithography creates neutral traps in the gate oxides of MOS devices, which may make these devices more sensitive...

Submicrometer Silicon MOSFET's fabricated using focused ion-beam lithography
1986 Edition, Volume 33, February 1, 1986 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Submicrometer n-channel enhancement-mode silicon MOSFET's with polysilicon gate lengths as small as 0.35 µm were fabricated using focused-ion-beam lithography. The polysilicon gate was patterned by a 80-kV Au-Si ion beam using a negative...

Deep-submicrometer MOS device fabrication using a photoresist-ashing technique
1988 Edition, Volume 9, April 1, 1988 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A photoresist-ashing process has been developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features. The ultrafine lines were obtained by calibrated ashing of the lithographically defined...

Patterning sub-30-nm MOSFET gate with i-line lithography
2001 Edition, Volume 48, May 1, 2001 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gates. These techniques require neither specific equipment nor materials. These can be used to fabricate experimental devices...

Transistor operations in 30-nm-gate-length EJ-MOSFETs
1997 Edition, January 1, 1997 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Discusses fabrication of electrically variable shallow junction MOSFETs (EJ-MOSFETs) to investigate transistor characteristics in ultra-fine gate MOSFETs. By using electron beam (EB) lithography and an ultra-high resolution resist (Calixarene), we could...

Advertisement