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0.0354mm 82μW 125KS/s 3-axis readout circuit for capacitive MEMS accelerometer
2013 Edition, November 1, 2013 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, we propose a power/area-efficient capacitive readout circuit for the Micro-Electro-Mechanical Systems (MEMS) sensor of 3-axis accelerometer. The proposed architecture is different from other traditional structures by exploiting...

A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a 12-bit 1-kS/s successive approximation register analog-to-digital converter (ADC) is presented for biomedical signal processing system. A multi-segmentation digital-to-analog converter architecture and a hybrid switching scheme are proposed to reduce the total unit...

A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing
2019 Edition, Volume 66, February 1, 2019 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

In this paper, a 12-bit 1-kS/s successive approximation register analog-to-digital converter (ADC) is presented for biomedical signal processing system. A multi-segmentation digital-to-analog converter architecture and a hybrid switching scheme are proposed to reduce the total unit...

A 43-nW 10-bit 1-kS/s SAR ADC in 180nm CMOS for biomedical applications
2015 Edition, November 1, 2015 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents an ultra-low power 10-bit, 1-KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. To achieve the nano-watt range power consumption, an ultra-low-power design technique has been utilized, inflicting maximum...

A 6.38 fJ/conversion 0.6V 0.43++W 100 kS/s 10-bit successive approximation ADC
2016 Edition, May 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This work presents a 10-bit successive approximation ADC for low voltage and low power applications. The chip operating voltage is 0.6 V with single-ended rail-to-rail swing input signal. Binary-weighted multilayer sandwich capacitor array is used in the digital to analog converter employed...

A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS
2016 Edition, Volume 63, March 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This brief describes a 14-b 10-kS/s successive approximation register analog-to-digital converter (ADC) for biomedical applications. In order to achieve enhanced linearity, a uniform-geometry nonbinary-weighted capacitive digital-to-analog converter is implemented. In addition,...

A 232-1996-kS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

Compressive sensing (CS) techniques enable new reduced-complexity designs for sensor nodes and help reduce overall transmission power in wireless sensor network. However, for real-time physiological signals monitoring, the orthogonal matching pursuit that applied prior CS...

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC
Volume PP - IEEE - Institute of Electrical and Electronics Engineers, Inc.

This paper presents an 11-bit ultralow voltage energy efficient successive approximation register (SAR) analog-to-digital converter (ADC). With the proposed semi-resting (SR) digital-to-analog convertor (DAC) switching scheme, this paper consumes only 6%-13.5% switching energy, compared to the...

A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter
1988 Edition, Volume 23, December 1, 1988 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A pipelined, 13-bit, 250-ksample/s (ks/s), 5-V, analog-to-digital (A/D) converter has been designed and fabricated in a 3- mu m, CMOS technology. Monotonicity is achieved using a reference-feedforward correction technique instead of (self-) calibration of trimming to minimize...

A 10-b 200-kS/s 250-nA Self-Clocked Coarse–Fine SAR ADC
2016 Edition, Volume 63, October 1, 2016 - IEEE - Institute of Electrical and Electronics Engineers, Inc.

A 10-b ultralow-power successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a standard 0.18- μm CMOS technology is described. The architecture consists of a coarse and a fine SAR ADC. The 2-b coarse SAR presets the two MSB capacitive arrays of the fine SAR,...

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