BEE2: a high-end reconfigurable computing system
Publisher: IEEE Computer Society
Authors:C. Chang; J. Wawrzynek; R.W. Brodersen
Year: 2005
Test solution selection using multiple-objective decision models and analyses
Publisher: IEEE Computer Society
Authors:D.T. Hamling
Year: 2005
Scalable processor instruction set extension
Publisher: IEEE Computer Society
Authors:J. Becker; A. Thomas
Year: 2005
B#: a battery emulator and power-profiling instrument
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Authors:C. Park; J. Liu; P.H. Chou
Year: 2005
Using a periodic square wave test signal to detect crosstalk faults
Publisher: IEEE Computer Society
Authors:Ming Shae Wu; Chung Len Lee
Year: 2005
Sharing standards work with Japan
Publisher: IEEE Computer Society
Authors:V. Berman
Year: 2005
The network is the chip
Publisher: IEEE Computer Society
Authors:G. Martin
Year: 2005
ITC 2004 panels: Part 1
Publisher: IEEE Computer Society
Authors:C. Stolicny
Year: 2005
DATC Newsletter
Publisher: IEEE Computer Society
Year: 2005
IEEE Computer Society Information
Publisher: IEEE Computer Society
Year: 2005
Déjà vu, all over again
Publisher: IEEE Computer Society
Authors:T. Kean
Year: 2005
From the EIC: The other face of design for manufacturability
Publisher: IEEE Computer Society
Year: 2005
Masthead
Publisher: IEEE Computer Society
Year: 2005
DAC Highlights
Publisher: IEEE Computer Society
Authors:A.B. Kahng; G. Martin
Year: 2005
Guest Editors' Introduction: DFM Drives Changes in Design Flow
Publisher: IEEE Computer Society
Authors:J. Carballo; Y. Zorian; R. Camposano; A.J. Strojwas; J.K. Kibarian; D. Wassung; A. Alexanian; S. Wigley; N. Kelly
Year: 2005
Some thoughts on the IC design-manufacture interface
Publisher: IEEE Computer Society
Authors:A.K. Wong
Year: 2005
Yield-driven, false-path-aware clock skew scheduling
Publisher: IEEE Computer Society
Authors:Jeng-Liang Tsai; Dong Hyun Baik; Chenm CC-P; K.K. Saluja
Year: 2005
Value-added defect testing techniques
Publisher: IEEE Computer Society
Authors:J. Jahangiri; D. Abercrombie
Year: 2005
Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below
Publisher: IEEE Computer Society
Authors:G. Yeric; E. Cohen; J. Garcia; K. Davis; E. Salem; G. Green
Year: 2005
New test paradigms for yield and manufacturability
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Authors:R. Madge
Year: 2005
Principles of sequential-equivalence verification
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Authors:M.N. Mneimneh; K.A. Sakallah
Year: 2005
Soft errors in advanced computer systems
Publisher: IEEE Computer Society
Authors:R. Baumann
Year: 2005
The future depends on innovation
Publisher: IEEE Computer Society
Year: 2005
Empowering the designer
Publisher: IEEE Computer Society
Authors:S. Sapatnekar
Year: 2005
TTTC recognizes test visionary's lifetime contribution
Publisher: IEEE Computer Society
Authors:T.W. Williams
Year: 2005
IEEE P1647 and P1800: two approaches to standardization and language design
Publisher: IEEE Computer Society
Authors:V. Berman
Year: 2005
Design Automation Technical Committee Newsletter
Publisher: IEEE Computer Society
Year: 2005
Computer Society Information
Publisher: IEEE Computer Society
Year: 2005
Nanotechnology: Where science of the small meets math of the large
Publisher: IEEE Computer Society
Authors:R. Gupta
Year: 2005
Masthead
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Year: 2005
IEEE Council for Electronic Design Automation: A new beginning
Publisher: IEEE Computer Society
Authors:G. De Micheli; A. Dunlop
Year: 2005
Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale
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Authors:R.I. Bahar; M.B. Tahoori; S.K. Shukla; F. Lombardi
Year: 2005
Recursive TMR: scaling fault tolerance in the nanoscale era
Publisher: IEEE Computer Society
Authors:D.D. Thaker; R. Amirtharajah; F. Impens; I.L. Chuang; F.T. Chong
Year: 2005
Seven strategies for tolerating highly defective fabrication
Publisher: IEEE Computer Society
Authors:A. DeHon; H. Naeimi
Year: 2005
A reconfiguration-based defect-tolerant design paradigm for nanotechnologies
Publisher: IEEE Computer Society
Authors:Chen He; M.F. Jacome; G. de Veciana
Year: 2005
Computer Society Information
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Year: 2005
Toward hardware-redundant, fault-tolerant logic for nanoelectronics
Publisher: IEEE Computer Society
Authors:Jie Han; J. Gao; P. Jonker; Yan Qi; J.A.B. Fortes
Year: 2005
New ECC for crosstalk impact minimization
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Authors:D. Rossi; C. Metra; A.K. Nieuwland; A. Katoch
Year: 2005
Precis: a usercentric word-length optimization tool
Publisher: IEEE Computer Society
Authors:M.L. Chang; S. Hauck
Year: 2005
Soft-spot analysis: targeting compound noise effects in nanometer circuits
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Authors:C. Zhao; S. Dey; X. Bai
Year: 2005
Modeling and analysis of parametric yield under power and performance constraints
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Authors:R.R. Rao; D. Blaauw; D. Sylvester; A. Devgan
Year: 2005
BIST the hard way
Publisher: IEEE Computer Society
Authors:S. Davidson
Year: 2005
Adding value to design and test through education: What are the challenges?
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Authors:L. Carro
Year: 2005
Conference Reports
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Year: 2005
Design Automation Technical Committee Newsletter
Publisher: IEEE Computer Society
Year: 2005
What's the problem?
Publisher: IEEE Computer Society
Authors:S. Davidson
Year: 2005
On-chip networks
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Authors:R. Gupta
Year: 2005
Masthead
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Year: 2005
Wireless, ESL, DFM, and Power on Stage at 42nd DAC
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Authors:G. Martin
Year: 2005
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research
Publisher: IEEE Computer Society
Authors:A. Ivanov; G. De Micheli
Year: 2005
Design, synthesis, and test of networks on chips
Publisher: IEEE Computer Society
Authors:P.P. Pande; C. Grecu; A. Ivanov; R. Saleh; G. De Micheli
Year: 2005
AEthereal network on chip: concepts, architectures, and implementations
Publisher: IEEE Computer Society
Authors:K. Goossens; J. Dielissen; A. Radulescu
Year: 2005
Analysis and implementation of practical, cost-effective networks on chips
Publisher: IEEE Computer Society
Authors:Se-Joong Lee; Kangmin Lee; Hoi-Jun Yoo
Year: 2005
Analysis of error recovery schemes for networks on chips
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Authors:S. Murali; T. Theocharides; N. Vijaykrishnan; M.J. Irwin; L. Benini; G. De Micheli
Year: 2005
Dynamic interconnection of reconfigurable modules on reconfigurable devices
Publisher: IEEE Computer Society
Authors:C. Bobda; A. Ahmadinia
Year: 2005
A reconfigurable manager for dynamically reconfigurable hardware
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Authors:J. Resano; D. Mozos; D. Verkest; F. Catthoor
Year: 2005
IEEE Computer Society Information
Publisher: IEEE Computer Society
Year: 2005
Tangram: virtual integration of IP components in a distributed cosimulation environment
Publisher: IEEE Computer Society
Authors:B.A. de Mello; U.R.F. Souza; J.K. Sperb; F.R. Wagner
Year: 2005
Verification by the pound
Publisher: IEEE Computer Society
Authors:G. Martin
Year: 2005
Conference Reports
Publisher: IEEE Computer Society
Year: 2005
Panel Summaries
Publisher: IEEE Computer Society
Year: 2005
An update on IEEE P1647: the e system verification language
Publisher: IEEE Computer Society
Authors:V. Berman
Year: 2005
DATC Newsletter
Publisher: IEEE Computer Society
Year: 2005
Masthead
Publisher: IEEE Computer Society
Year: 2005
Going 3D: Silicon and D&T
Publisher: IEEE Computer Society
Authors:R. Gupta
Year: 2005
Guest Editors' Introduction: New Dimensions in 3D Integration
Publisher: IEEE Computer Society
Authors:S. Sapatnekar; K. Nowka
Year: 2005
Demystifying 3D ICs: the pros and cons of going vertical
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Authors:W.R. Davis; J. Wilson; S. Mick; J. Xu; H. Hua; C. Mineo; A.M. Sule; M. Steer; P.D. Franzon
Year: 2005
3D chip stack technology using through-chip interconnects
Publisher: IEEE Computer Society
Authors:P. Benkart; A. Kaiser; A. Munding; M. Bschorr; H.-J. Pfleiderer; E. Kohn; A. Heittmann; H. Huebner; U. Ramacher
Year: 2005
Placement and routing in 3D integrated circuits
Publisher: IEEE Computer Society
Authors:C. Ababei; Y. Feng; B. Goplen; Hushrav Mogal; T. Zhang; K. Bazargan; Sachin Sapatnekar
Year: 2005
Physical design for 3D system on package
Publisher: IEEE Computer Society
Authors:S.K. Lim
Year: 2005
Predicting the performance of a 3D processor-memory chip stack
Publisher: IEEE Computer Society
Authors:P. Jacob; O. Erdogan; A. Zia; P.M. Belemjian; R.P. Kraft; J.F. McDonald
Year: 2005
First-order performance prediction of cache memory with wafer-level 3D integration
Publisher: IEEE Computer Society
Authors:A. Zeng; J. Lu; K. Rose; R.J. Gutmann
Year: 2005
Bridging the processor-memory performance gap with 3D IC technology
Publisher: IEEE Computer Society
Authors:C.C. Liu; I. Ganusov; M. Burtscher; Sandip Tiwari
Year: 2005
Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive
Publisher: IEEE Computer Society
Authors:S. Davidson
Year: 2005
X-tolerant test response compaction
Publisher: IEEE Computer Society
Authors:Subhasish Mitra; M. Mitzenmacher; S.S. Lumetta; Nishant Patil
Year: 2005
A novel transition fault ATPG that reduces yield loss
Publisher: IEEE Computer Society
Authors:X. Liu; M.S. Hsiao
Year: 2005
IC outlier identification using multiple test metrics
Publisher: IEEE Computer Society
Authors:S.S. Sabade; D.M. Walker
Year: 2005
Designing "Vary" Good Circuitry
Publisher: IEEE Computer Society
Authors:S. Sapatnekar
Year: 2005
Panel Summaries
Publisher: IEEE Computer Society
Year: 2005
2005 IEEE East-West Design and Test Workshop
Publisher: IEEE Computer Society
Authors:V. Hahanov
Year: 2005
Computer Society Information
Publisher: IEEE Computer Society
Year: 2005
Test Technology TC Newsletter
Publisher: IEEE Computer Society
Year: 2005
IEEE Design & Test of Computers, 2005 Annual Index, Volume 22
Publisher: IEEE Computer Society
Year: 2005
ITC is Cool
Publisher: IEEE Computer Society
Authors:R.C. Aitken
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Call for Papers
Publisher: IEEE Computer Society
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Masthead
Publisher: IEEE Computer Society
Year: 2006
New beginnings, continued success
Publisher: IEEE Computer Society
Authors:Kwang-Ting Tim Cheng
Year: 2006
advertisement
Publisher: IEEE Computer Society
Year: 2006
Automated source-level error localization in hardware designs
Publisher: IEEE Computer Society
Authors:B. Peischl; F. Wotawa
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MOSFET mismatch modeling: a new approach
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Authors:H. Klimach; A. Arnaud; C. Galup-Montoro; M.C. Schneider
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Logic design for printability using OPC methods
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Early, accurate dependability analysis of CAN-based networked systems
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Source-synchronous testing of multilane PCI Express and HyperTransport buses
Publisher: IEEE Computer Society
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Efficient parametric fault detection in switched-capacitor filters
Publisher: IEEE Computer Society
Authors:A. Petraglia; J.M. Canive; M.R. Petraglia
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Searching for clues: Diagnosing IC failures
Publisher: IEEE Computer Society
Authors:S. Davidson
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Embedded systems and the kitchen sink
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Authors:C. Songer
Year: 2006
Conference Reports: 2005 International Test Conference
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Authors:K. Butler
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IEEE Computer Society Digital Library Packages for Institutions
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Year: 2006
TTTC Newsletter
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Year: 2006
DATC Newsletter
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Year: 2006
IEEE Computer Society Information
Publisher: IEEE Computer Society
Year: 2006
All about getting it
Publisher: IEEE Computer Society
Authors:S. Davidson
Year: 2006
[Inside front cover]
Publisher: IEEE Computer Society
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Call for Papers
Publisher: IEEE Computer Society
Year: 2006
Masthead
Publisher: IEEE Computer Society
Year: 2006
Dealing with early life failures
Publisher: IEEE Computer Society
Authors:Kwang-Ting Tim Cheng
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Guest Editor's Introduction: Evolving Methods for Detecting and Handling Reliability Defects
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Reducing burn-in time through high-voltage stress test and Weibull statistical analysis
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Call-for-Papers
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Combining negative binomial and Weibull distributions for yield and reliability prediction
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Call for Papers
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The impact of multiple failure modes on estimating product field reliability
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Call for Papers
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Test consideration for nanometer-scale CMOS circuits
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Year: 2006
Optical contactless probing: an all-silicon, fully optical approach
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Authors:S. Sayil
Year: 2006
IEEE Computer Society Information
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Year: 2006
A SystemC refinement methodology for embedded software
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Authors:J. Chevalier; M. de Nanclas; L. Filion; O. Benny; M. Rondonneau; G. Bois; El Mostapha Aboulhamid
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Call for Papers
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Year: 2006
Was it worth the wait? Yes!
Publisher: IEEE Computer Society
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An insider's look at microprocessor design
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Authors:S. Davidson
Year: 2006
ITC 2005 panels
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Authors:C. Stolicny
Year: 2006
TTTC technical forum honoring Sudhakar M. Reddy
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CEDA Currents
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Authors:K. Mayaram
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TTTC Newsletter
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Year: 2006
Making more out of open-source tools
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Authors:B. West
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[Inside front cover]
Publisher: IEEE Computer Society
Year: 2006
IEEE Computer Society Celebrates Two 60-Year Anniversaries
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Masthead
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Year: 2006
The Need for a SiP Design and Test Infrastructure
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Authors:Kwang-Ting Cheng
Year: 2006
DAC Highlights
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Authors:S. Sapatnekar; G. Martin
Year: 2006
2006 Latin American Test Workshop
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Guest Editors' Introduction: Big Innovations in Small Packages
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Cell phone integration: SiP, SoC, and PoP
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Chip-package codesign flow for mixed-signal SiP designs
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System-in-package testing: problems and solutions
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Packaging a 40-Gbps serial link using a wire-bonded plastic ball grid array
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Electronic system, platform, and package codesign
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A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs
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IEEE Computer Society Membership Information
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IEEE Computer Society Information
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The First Transaction, but not the Last
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Test Technology Technical Council Newsletter
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Advertiser/Product Index
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IEEE Computer Society Digital Library Packages for Institutions
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Is System in Package the Panacea for Integration?
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[Inside back cover]
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[Inside front cover]
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IEEE Computer Society Celebrates Two 60-Year Anniversaries
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Masthead
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Vision from the Top
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On-Chip Testing Techniques for RF Wireless Transceivers
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Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
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Survey of Test Vector Compression Techniques
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Sociology of Design and EDA
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IEEE Computer Society Information
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IEEE Computer Society Membership Information
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Panel Summaries: Real-Time Volume Diagnostics--Requirements and Challenges
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Standards: The P1685 IP-XACT IP Metadata Standard
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Book Reviews: Plumbing the Depths of Leakage
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Test Technology TC Newsletter
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CEDA Currents
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IEEE Computer Society Digital Library Packages for Institutions
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Who Reads This Stuff Anyway?
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[Back cover]
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[Inside front cover]
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IEEE Computer Society Celebrates Two 60-Year Anniversaries
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The New World of ESL Design
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IEEE Computer Society Digital Library Packages for Institutions
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Guest Editors' Introduction: The True State of the Art of ESL Design
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A Component-Based Design Environment for ESL Design
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Modeling Embedded Systems: From SystemC and Esterel to DFCharts
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A Platform-Based Taxonomy for ESL Design
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The Challenges of Synthesizing Hardware from C-Like Languages
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A Different View: Hardware Synthesis from SystemC is a Maturing Technology
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Guest Editor's Introduction: ITC Helps Get More Out of Test
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Extracting Defect Density and Size Distributions from Product ICs
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Improving Transition Delay Test Using a Hybrid Method
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Impact of Thermal Gradients on Clock Skew and Testing
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Test Technology TC Newsletter
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Book Reviews: A Comprehensive EDA Handbook
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Standards: DASC sees moves toward formality in design
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CEDA Currents
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IEEE Computer Society ReadyNotes Information
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Handling variations and uncertainties
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Masthead
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Guest Editors' Introduction: Process Variation and Stochastic Design and Test
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Testing On-Die Process Variation in Nanometer VLSI
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Statistical Test Compaction Using Binary Decision Trees
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Call for Papers
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A DFT Approach for Testing Embedded Systems Using DC Sensors
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Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design
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ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
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Call for Papers
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An Exciting Time in Engineering
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Book Reviews: NoC, NoC ... Who's there?
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Design and test on chip for EMC
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East-West Design & Test Workshop
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CEDA Currents
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TTTC Newsletter
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DATC Newsletter
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IEEE Computer Society Information
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IEEE Design & Test of Computers 2006 Annual Index, Volume 23
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Tackling variability and reliability challenges
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IEEE Computer Society Information
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Moore's law meets the life sciences
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[Masthead]
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A. Richard Newton: Technologist with a Mission
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Guest Editors' Introduction: Biochips and Integrated Biosensor Platforms
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Advertisers/Product Index
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Lab on a Chip for Live-Cell Manipulation
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IEEE Computer Society Information
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Electronic Detection of DNA Hybridization: Toward CMOS Microarrays
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Call for Papers: The Current State of Test Compression
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Simulation-Based Analysis of Dielectrophoretic Field Flow Fractionation Devices
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Call for Papers: Special Issue on Design and Test of RFIC Chips
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Computer-Aided Design and Test for Digital Microfluidics
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IEEE Distributed Systems Online - Information
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Testing Microelectronic Biofluidic Systems
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Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs
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ITC 2006 panels
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TTTC Newsletter
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Conflicting International Standards Pressure Chip Designers
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CEDA Currents
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Embedded Systems Week
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DATC Newsletter
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A laboratory right under your nose
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IEEE Computer Society Digital Library
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IEEE Computer Society Membership Information
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Call for Papers: Special Issue on Design and Test of RFIC Chips
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Cocktail approach to functional verification
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[Masthead]
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Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques
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A Survey of Hybrid Techniques for Functional Verification
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Hybrid Verification of Protocol Bridges
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Combining Theorem Proving with Model Checking through Predicate Abstraction
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Hybrid, Incremental Assertion-Based Verification for TLM Design Flows
Publisher: IEEE Computer Society
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Hybrid Approach to Faster Functional Verification with Full Visibility
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Economic Aspects of Memory Built-in Self-Repair
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Roundtable: Envisioning the Future for Multiprocessor SoC
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FSA SiP Market and Patent Analysis Report
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On the cusp of a validation wall
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Test Technology TC Newsletter
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Losing control
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Call for Papers: Special Issue on Design and Test of RFIC Chips
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Supporting cost-effective innovation
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Year: 2007
[Masthead]
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Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs
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A Production IR-Drop Screen on a Chip
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Call for Papers: The Current State of Test Compression
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Modeling Power Supply Noise in Delay Testing
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Power Supply Noise in SoCs: Metrics, Management, and Measurement
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Call for Papers: Special Issue on Silicon Debugging and Diagnosis
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Power Grid Physics and Implications for CAD
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Analysis of Power Supply Noise in the Presence of Process Variations
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Software 2007 Editorial Calendar
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Scan-Based Tests with Low Switching Activity
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Power Droop Testing
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The case for power with test
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Design and CAD for Nanotechnologies
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Guest Editors' Introduction: The State of the Art in Nanoscale CAD
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An Overview of Nanoscale Devices and Circuits
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Tracking Uncertainty with Probabilistic Logic Circuit Testing
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Leakage Minimization Technique for Nanoscale CMOS VLSI
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Practices in Mixed-Signal and RF IC Testing
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Crosstalk- and SEU-Aware Networks on Chips
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ACID: Automatic Sort-Map Classification for Interactive Process Diagnosis
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Empirical Validation of Yield Recovery Using Idle-Cycle Insertion
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Variation-Tolerant, Power-Safe Pattern Generation
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Raisin: Redundancy Analysis Algorithm Simulation
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How do we train today's students to become tomorrow's engineers?
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Combining synchronous and asynchronous timing schemes for high-performance systems
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Guest Editors' Introduction: GALS Design and Validation
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A Survey and Taxonomy of GALS Design Styles
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Computing in Science and Engineering 2007 Editorial Calendar
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Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
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Adaptive Latency-Insensitive Protocols
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IEEE Software 2007 Editorial Calendar
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A GALS Infrastructure for a Massively Parallel Multiprocessor
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A Highly Scalable GALS Crossbar Using Token Ring Arbitration
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Guest Editor's Introduction: Getting More Out of Test
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X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
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Cell Broadband Engine Debugging for Unknown Events
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Authors:M.W. Riley; M. Genden
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The Psychology of Electronic Test
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DAC Highlights
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Book Reviews: Test Tutorials in Book Form
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DATE 07 workshop on diagnostic services in NoCs
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ITC exhibits for fun and profit
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Trustworthy ICs for secure embedded computing
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[Masthead]
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Guest Editors' Introduction: Security and Trust in Embedded-Systems Design
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Call for Papers
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A Survey of Lightweight-Cryptography Implementations
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OEM Component Authentication
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Power Analysis Attacks and Countermeasures
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Faults, Injection Methods, and Fault Attacks
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Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
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Security-Performance Trade-offs in Embedded Systems Using Flexible ECC Hardware
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Aegis: A Single-Chip Secure Processor
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Security in SRAM FPGAs
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Implementing Embedded Security on Dual-Virtual-CPU Systems
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Protecting Critical Data
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DASC standards track IP-based design trends
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Making a List...Checking it Twice
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IEEE Design & Test of Computers: 2007 Annual Index, Volume 24
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Tesla and AND gates
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IEEE Design & Test Call for Papers
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From the EIC
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Year: 2008
[Masthead]
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Guest Editors' Introduction: The Evolution of RFIC Design and Test
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Authors:Bruce C. Kim; Craig Force
Year: 2008
Build Your Career [advertisement]
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Design and Analysis of a Transversal Filter RFIC in SiGe Technology
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Year: 2008
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Design of a Low-Noise UWB Transceiver SiP
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Decreasing Test Qualification Time in AMS and RF Systems
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Light-Enhanced FET Switch Improves ATE RF Power Settling
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Authors:J. Kelly; E. Lowery; D. Nicholson; V. Grothen
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Time-Division-Multiplexed Test Delivery for NoC Systems
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Low-Impact Processor for Dynamic Runtime Power Management
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Hybrid-SBST Methodology for Efficient Testing of Processor Cores
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Simultaneous Switching Noise: The Relation between Bus Layout and Coding
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In Conversation with Tensilica CEO Chris Rowen
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DATC Newsletter
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TTTC Newsletter
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Changing times in the RF world
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Test compression saves bits, cycles, and money
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[Masthead]
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Guest Editors' Introduction: Progress in Test Compression
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Historical Perspective on Scan Compression
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VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG
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UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting
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Distributed Systems Online [advertisement]
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Hierarchical Test Compression for SoC Designs
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Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers
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Wireless System for Microwave Test Signal Generation
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Software 2008 Editorial Calendar
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An Illustrated Methodology for Analysis of Error Tolerance
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Device Model for Ballistic CNFETs Using the First Conducting Band
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DATC Newsletter
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Discussing DRAM and CMOS Scaling with Inventor Bob Dennard
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Standards update from IP 07
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TTTC Newsletter
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The commonality of vector generation techniques
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sensors expo and conference information
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Build Your Career in Computing [advertisement]
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Effective silicon debug is key for time to money
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[Masthead]
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Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis
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Functional Debug Techniques for Embedded Systems
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In-System Silicon Validation and Debug
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Case Study on Speed Failure Causes in a Microprocessor
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Linking Statistical Learning to Diagnosis
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Survey of Scan Chain Diagnosis
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Physical Techniques for Chip-Backside IC Debug in Nanotechnologies
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Overview of Debug Standardization Activities
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IEEE Computer Society Membership and Subscriptions form
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IEEE Distributed Systems Online [advertisement]
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Thousand-Core Chips [Roundtable]
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TTTC Newsletter
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Bugs, moths, grasshoppers, and whales
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Build Your Career in Computing [advertisement]
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Not just research as usual
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[Masthead]
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Guest Editors' Introduction: System IC Design Challenges beyond 32 nm
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Challenges and Solutions for Late- and Post-Silicon Design
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Interview: A Discussion with Intel Chair Craig Barrett
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The Concurrency Challenge
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The GSRC: Bridging Academia and Industry
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Reliable Systems on Unreliable Fabrics
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The Search for Alternative Computational Paradigms
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Variability and New Design Paradigms
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Is a Unified Methodology for System-Level Design Possible?
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Workloads of the Future
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The GSRC's Role in Meeting Tomorrow's Design Challenges
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Computing Now
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A Digital-Microfluidic Approach to Chip Cooling
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With pick and shovel through our data
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DATC Newsletter
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IEEE Intelligent Systems 2008 Editorial Calendar
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IEEE Pervasive Computing [advertisement]
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TTTC Newsletter
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call-for-papers
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Special Issue on High-Level Synthesis
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Interconnect challenges in the multicore era
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Staff listing
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ITC 2008 Highlights
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Guest Editors' Introduction: Tackling Key Problems in NoCs
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COSI: A Framework for the Design of Interconnection Networks
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A Quality-Driven Design Approach for NoCs
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Characterization of Equalized and Repeated Interconnects for NoC Applications
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