IEEE - Institute of Electrical and Electronics Engineers, Inc. - A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI

Author(s): Shichijo, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1981
Conference Location: Washington, DC, USA, USA
Conference Date: 7 December 1981
Page(s): 219 - 222
DOI: 10.1109/IEDM.1981.190046
Regular:

The device performance of scaled n-channel and p-channel MOS devices is theoretically examined in detail down to 0.2 µm gate length including all of the major effects such as source/ drain series... View More

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