IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Optimized ATPG

Author(s): Mourad, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1980
Conference Location: Minneapolis, MN, USA, USA
Conference Date: 23 June 1980
Page(s): 381 - 385
ISBN (Paper): 0-89791-020-6
DOI: 10.1109/DAC.1980.1585275
Regular:

This paper describes a hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur. The failure probabilities of the nodes of a board are... View More

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