Bulk Processing in Distributed Logic Memory

Author(s): B. A. Crane ; J. A. Githens
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 1965
Volume: EC-14
Page(s): 186 - 196
ISSN (Paper): 0367-7508
DOI: 10.1109/PGEC.1965.263964



Use of a content-addressable memory as a highly parallel digital computer is described. The ability to perform any arithmetic operation on many sets of data at the same time is shown. The memory organization and the storage of data are such that many operations are performed parallel by bit as well as parallel by word, resulting in more efficient algorithms and shorter execution times. Consideration of the limitations of a linear memory array in performing such operations leads to the description of a more efficient organization, called the two-dimensional distributed logic memory. The efficiency of this form in the bulk processing of data is illustrated by a number of algorithms for basic data processing operations, including matrix inversion.